Commit Graph

72788 Commits

Author SHA1 Message Date
Eric Christopher
51ff48ad30 Fix an off by one error.
Part of rdar://9037836 and rdar://9119939

llvm-svn: 132590
2011-06-03 20:44:52 +00:00
Bill Wendling
f78358d1e7 Remove testcase. It's problematic for the buildbots.
llvm-svn: 132589
2011-06-03 20:43:58 +00:00
Jakob Stoklund Olesen
449aaba5b0 Switch AllocationOrder to using RegisterClassInfo instead of a BitVector
of reserved registers.

Use RegisterClassInfo in RABasic as well. This slightly changes som
allocation orders because RegisterClassInfo puts CSR aliases last.

llvm-svn: 132581
2011-06-03 20:34:53 +00:00
Jakob Stoklund Olesen
e345312955 Preserve the original ordering when a CSR has multiple aliases.
Previously, these aliases would be ordered alphabetically. (BH, BL)

Print out the computed allocation orders.

llvm-svn: 132580
2011-06-03 20:34:50 +00:00
Dan Gohman
6d082aec26 When merging MustAlias and PartialAlias, chose PartialAlias instead
of conservatively choosing MayAlias.

llvm-svn: 132579
2011-06-03 20:17:36 +00:00
Devang Patel
ec747bb76b Use IRBuilder, preserve line numbers.
llvm-svn: 132578
2011-06-03 19:46:19 +00:00
Bill Wendling
08a7654503 Accomodate front-ends which use private instead of internal here.
llvm-svn: 132575
2011-06-03 19:21:05 +00:00
Eric Christopher
e831655dd9 Make the Uv constraint a memory operand. This doesn't solve the
addressing mode problem mentioned in r132559.

Backend part of rdar://9037836 and part of rdar://9119939

llvm-svn: 132561
2011-06-03 17:24:37 +00:00
Eric Christopher
e446e0fdb9 Add a TODO about memory operands.
llvm-svn: 132559
2011-06-03 17:21:23 +00:00
Hans Wennborg
fc0acdb90f Test commit.
llvm-svn: 132558
2011-06-03 17:15:37 +00:00
Devang Patel
e3190a1377 A typedef's context is not the same as type's context. It is the context of typedef decl itself. Use extra parameter to communicate this to DIBuilder.
llvm-svn: 132556
2011-06-03 17:04:51 +00:00
Chad Rosier
3dd747f5a1 Revert name change from r132533. Lower case naming was intended per style guidelines.
llvm-svn: 132555
2011-06-03 17:02:19 +00:00
Roman Divacky
3624922127 Fix wrong usages of CTR/MCTR where CTR8/MCTR8 was meant.
- Check for MTCTR8 in addition to MTCTR when looking up a hazard.

- When lowering an indirect call use CTR8 when targeting 64bit.

- Introduce BCTR8 that uses CTR8 and use it on 64bit when expanding ISD::BRIND.

The last change fixes PR8487. With those changes, we are able to compile a
running "ls" and "sh" on FreeBSD/PowerPC64.

llvm-svn: 132552
2011-06-03 15:47:49 +00:00
Zhongxing Xu
10e41c48ee singed int causes signed extension, which contradicts the intention to pick up
integers with high 32 bits being zero.

llvm-svn: 132538
2011-06-03 08:29:51 +00:00
Nick Lewycky
73b6cfd90c Rework the logic to not rely on undefined behaviour (1LL << 64). Also simplify.
llvm-svn: 132537
2011-06-03 08:25:39 +00:00
Nick Lewycky
ce38535f5b Bail on unswitching a switch statement for a case with a critical edge. We name
which edge to split by pred/succ pair, which means that we can end up splitting
the wrong edge (by case value) in the switch statement entirely. Fixes PR10031!

llvm-svn: 132535
2011-06-03 06:27:15 +00:00
Chad Rosier
8b97de1cfa Whitespace and other cleanup. Functionallity unchanged.
llvm-svn: 132533
2011-06-03 05:09:12 +00:00
Charles Davis
8154eea248 Treat Win64 EH as a DWARF EH scheme. For GCC-style exceptions, the layout of
the handler's data area is similar to a DWARF-format LSDA. (It is, in fact,
a 32-bit pointer to the personality routine followed by the DWARF LSDA.)

llvm-svn: 132532
2011-06-03 05:09:12 +00:00
Andrew Trick
e9e48acf00 Corrections and additional information for "Creating and LLVM Project"
documentation. This should now reflect the current state of LLVM Makefiles.

llvm-svn: 132527
2011-06-03 02:20:48 +00:00
Andrew Trick
fa7de8e32b whitespace
llvm-svn: 132526
2011-06-03 02:16:53 +00:00
Eli Friedman
eae10d6163 Add ARM fast-isel support for materializing the address of a global in cases where the global uses an indirect symbol.
rdar://9431157

llvm-svn: 132522
2011-06-03 01:13:19 +00:00
Andrew Trick
39b3306530 Basic PassManager diagnostics.
Added asserts whenever attempting to use a potentially
uninitialized pass. This helps people trying to develop a new pass and
people trying to understand the bug reports filed by the former people.

llvm-svn: 132520
2011-06-03 00:48:58 +00:00
Andrew Trick
335c4f8d8b whitespace
llvm-svn: 132519
2011-06-03 00:44:32 +00:00
Andrew Trick
4db3dc6d19 Test case pasto (failed when run with IR verifier).
llvm-svn: 132516
2011-06-02 23:57:27 +00:00
Jakob Stoklund Olesen
9037bbb219 Avoid calling TRI->getAllocatableSet in RAFast.
When compiling a program with lots of small functions like
483.xalancbmk, this makes RAFast 11% faster.

Add some comments to clarify the difference between unallocatable and
reserved registers. It's quite subtle.

The fast register allocator depends on EFLAGS' not being allocatable on
x86. That way it can completely avoid tracking liveness, and it won't
mind when there are multiple uses of a single def.

llvm-svn: 132514
2011-06-02 23:41:40 +00:00
Eric Christopher
d68494ffdd Have LowerOperandForConstraint handle multiple character constraints.
Part of rdar://9119939

llvm-svn: 132510
2011-06-02 23:16:42 +00:00
Jakob Stoklund Olesen
409986a648 Flag unallocatable register classes instead of giving them empty
allocation orders.

llvm-svn: 132509
2011-06-02 23:07:24 +00:00
Jakob Stoklund Olesen
4f76a2bdc8 Make it possible to have unallocatable register classes.
Some register classes are only used for instruction operand constraints.
They should never be used for virtual registers. Previously, those
register classes were given an empty allocation order, but now you can
say 'let isAllocatable=0' in the register class definition.

TableGen calculates if a register is part of any allocatable register
class, and makes that information available in TargetRegisterDesc::inAllocatableClass.

The goal here is to eliminate use cases for overriding allocation_order_*
methods.

llvm-svn: 132508
2011-06-02 23:07:20 +00:00
Devang Patel
73e16acee8 Preserve line number information while converting Invoke into a Call.
llvm-svn: 132505
2011-06-02 22:46:58 +00:00
Bill Wendling
6020896a6e This should have been a C++ testcase.
llvm-svn: 132504
2011-06-02 22:26:15 +00:00
Jakob Stoklund Olesen
52c6a75ee3 Just use a SmallVector.
I was confused whether new uint8_t[] would zero-initialize the returned
array, and it seems that so is gcc-4.0.

This should fix the test failures on darwin 9.

llvm-svn: 132500
2011-06-02 22:22:43 +00:00
Bill Wendling
854ec415ea Testcase for r132493.
llvm-svn: 132495
2011-06-02 22:12:42 +00:00
Bill Wendling
8988d1f21f Update for r132493 change.
llvm-svn: 132494
2011-06-02 22:11:49 +00:00
Devang Patel
7b9fc618b2 Remove dead code.
llvm-svn: 132488
2011-06-02 21:31:00 +00:00
Devang Patel
6455c3f6ae Update DBG_VALUEs while breaking anti dependencies.
llvm-svn: 132487
2011-06-02 21:26:52 +00:00
Tanya Lattner
aa1f6df650 Fix encoding for VEXTdf.
llvm-svn: 132486
2011-06-02 21:25:24 +00:00
Eli Friedman
0db9c60959 PR10067: Add missing safety check to call return transformation in MemCpyOpt::processStore. If something accesses the dest of the "copy" between the call and the copy, the performCallSlotOptzn transformation is not valid.
llvm-svn: 132485
2011-06-02 21:24:42 +00:00
Devang Patel
1c30f3ac27 During post RA scheduling, do not try to chase reg defs. to preserve DBG_VALUEs. This approach has several downsides, for example, it does not work when dbg value is a constant integer, it does not work if reg is defined more than once, it places end of debug value range markers in the wrong place. It even causes misleading incorrect debug info when duplicate DBG_VALUE instructions point to same reg def.
Instead, use simpler approach and let DBG_VALUE follow its predecessor instruction. After live debug value analysis pass, all DBG_VALUE instruction are placed at the right place. Thanks Jakob for the hint!

llvm-svn: 132483
2011-06-02 20:07:12 +00:00
Rafael Espindola
2eab5458f6 Add test for PR10068.
llvm-svn: 132482
2011-06-02 20:02:48 +00:00
Rafael Espindola
1299f014d4 Revert 132424 to fix PR10068.
llvm-svn: 132479
2011-06-02 19:57:47 +00:00
Stuart Hastings
bf1b4a2e2e Andy pointed out a dumb omission in this test case. Thanks Andy!
llvm-svn: 132477
2011-06-02 19:26:49 +00:00
Eric Christopher
0c337a44e9 Add a new parse hint for multi-letter constraints in inline asm.
Testcase will come when we use it.

Part of rdar://9119939

llvm-svn: 132476
2011-06-02 19:26:37 +00:00
Stuart Hastings
af7e57f485 Jakob pointed out a dumb omission in this test case. Thanks Jakob!
llvm-svn: 132472
2011-06-02 18:44:05 +00:00
Jakob Stoklund Olesen
b5392437c8 Use RegisterClassInfo::getOrder in RAFast.
This saves two virtual function calls and an Allocatable BitVector test,
making RAFast run 2% faster.

llvm-svn: 132471
2011-06-02 18:35:30 +00:00
Jim Grosbach
8a7731f951 .cfi directive register parsing flexibility.
Parsing a register name/number for .cfi directives can't assume that a
register name starts with a '%' token. Be more flexible and check for a
register number instead. Still unlikely to be perfect, but it allows us
to parse both plain identifiers as register names and integers as register
numbers, which is what we're wanting to support at this point.

llvm-svn: 132466
2011-06-02 17:14:04 +00:00
Stuart Hastings
8447f18f85 Omit unnecessary stack copy when x87 input is a load.
rdar://problem/6373334

llvm-svn: 132458
2011-06-02 15:57:11 +00:00
Benjamin Kramer
e149500163 Start with a zeroed CSRNum map.
Found by valgrind.

llvm-svn: 132457
2011-06-02 12:07:44 +00:00
Jakob Stoklund Olesen
a8db700d44 Initialize members to fix problem found by valgrind.
llvm-svn: 132456
2011-06-02 05:43:49 +00:00
Jakob Stoklund Olesen
25716baae0 Use TRI::has{Sub,Super}ClassEq() where possible.
No functional change.

llvm-svn: 132455
2011-06-02 05:43:46 +00:00
Stuart Hastings
cf5c3fdc33 Tweak testcase for ARM bot. rdar://problem/5993888
llvm-svn: 132454
2011-06-02 05:05:39 +00:00