14950 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
3eaaa93104 Remove the -color-ss-with-regs option.
It was off by default.

The new register allocators don't have the problems that made it
necessary to reallocate registers during stack slot coloring.

llvm-svn: 144481
2011-11-13 00:31:23 +00:00
Jakob Stoklund Olesen
d0ddec5771 Delete the 'standard' spiller with used the old spilling framework.
The current register allocators all use the inline spiller.

llvm-svn: 144477
2011-11-12 23:29:02 +00:00
Jakob Stoklund Olesen
bb527a67c0 Remove histogram tests.
Counting the number of occurences of each opcode is not a useful test.

llvm-svn: 144474
2011-11-12 22:39:40 +00:00
Jakob Stoklund Olesen
9195bec6e7 RAGreedy is better about hinting now.
Or maybe we are just getting lucky.

llvm-svn: 144473
2011-11-12 22:39:37 +00:00
Jakob Stoklund Olesen
4aa9c6888f Linear scan is going away.
llvm-svn: 144472
2011-11-12 22:39:34 +00:00
Jakob Stoklund Olesen
e1b1bbb882 XFAIL test that depends on linear scan to remove dead code.
Filed PR11364 to track the problem.  Should the register allocator
eliminate dead code?

llvm-svn: 144471
2011-11-12 22:39:30 +00:00
Jakob Stoklund Olesen
43b7a3871b Remove obsolete test.
This test was committed with a bugfix to RemoveCopyByCommutingDef, but
that optimization is no longer triggered by this test.

llvm-svn: 144470
2011-11-12 22:39:27 +00:00
Jakob Stoklund Olesen
6a290484cb Remove obsolete test.
This test is for a very specific LocalRewriter bug.  LocalRewriter is
going away.

llvm-svn: 144469
2011-11-12 22:39:24 +00:00
Jakob Stoklund Olesen
005eabf28a Remove obsolete test.
I don't think this test does what is was supposed to do, and
LocalRewriter is going away anyway.

llvm-svn: 144463
2011-11-12 20:37:57 +00:00
Jakob Stoklund Olesen
c11d7a9b4d Eliminate more linear scan tests.
llvm-svn: 144462
2011-11-12 20:35:26 +00:00
Jakob Stoklund Olesen
0fe59856fd Switch a couple -O0 tests to RABasic.
llvm-svn: 144461
2011-11-12 20:11:04 +00:00
Jakob Stoklund Olesen
94ce588b20 Switch a few tests off linearscan.
llvm-svn: 144460
2011-11-12 19:53:52 +00:00
Jakob Stoklund Olesen
f8fed2a3a7 Delete old test of a VirtRegRewriter feature.
This test doesn't expose the issue with RAGreedy.

I filed PR11363 to track the missing InlineSpiller feature.

llvm-svn: 144459
2011-11-12 19:53:48 +00:00
Jakob Stoklund Olesen
49118cf9a5 Remove old test that doesn't make sense.
The test is checking that the output doesn't contains any 'mov '
strings. It does contain movl, though.

llvm-svn: 144458
2011-11-12 19:53:45 +00:00
Craig Topper
0458cdf64a Add more AVX2 shift lowering support. Move AVX2 variable shift to use patterns instead of custom lowering code.
llvm-svn: 144457
2011-11-12 09:58:49 +00:00
Nick Lewycky
772024a00d Don't try to loop on iterators that are potentially invalidated inside the loop. Fixes PR11361!
llvm-svn: 144454
2011-11-12 03:09:12 +00:00
Eli Friedman
a83fbaff5f Make sure scalarrepl picks the correct alloca when it rewrites a bitcast. Fixes PR11353.
llvm-svn: 144442
2011-11-12 02:07:50 +00:00
Rafael Espindola
5f6b14719f The dwarf standard says that the only differences between a out-of-line
instance and a concrete inlined instance are the use of DW_TAG_subprogram
instead of DW_TAG_inlined_subroutine and the who owns the tree.

We were also omitting DW_AT_inline from the abstract roots. To fix this,
make sure we mark abstract instance roots with DW_AT_inline even when
we have only out-of-line instances referring to them with DW_AT_abstract_origin.

FileCheck is not a very good tool for tests like this, maybe we should add
a -verify mode to llvm-dwarfdump.

llvm-svn: 144441
2011-11-12 01:57:54 +00:00
Eli Friedman
8563e57e38 Don't try to form pre/post-indexed loads/stores until after LegalizeDAG runs. Fixes PR11029.
llvm-svn: 144438
2011-11-12 00:35:34 +00:00
Jim Grosbach
13b7ab7527 ARM optional size suffix for VLDR/VSTR syntax.
llvm-svn: 144427
2011-11-11 23:34:43 +00:00
Chad Rosier
a2a0fbeded Add support in fast-isel for selecting memset/memcpy/memmove intrinsics.
llvm-svn: 144426
2011-11-11 23:31:03 +00:00
Chad Rosier
88ab27405f Loosen test by using REs. Approved by Devang.
llvm-svn: 144425
2011-11-11 23:25:38 +00:00
Andrew Trick
6ff75a5d8d Preserve MachineMemOperands in ARMLoadStoreOptimizer.
Fixes PR8113.

llvm-svn: 144409
2011-11-11 22:18:09 +00:00
Jim Grosbach
1d581ecb00 ARM allow Q registers in vldm/vstm register lists.
rdar://9672822

llvm-svn: 144407
2011-11-11 21:27:40 +00:00
Devang Patel
09f4f9890c Move X86 specific test in X86 directory.
llvm-svn: 144395
2011-11-11 18:13:19 +00:00
Devang Patel
a804f1a297 Move X86 specific test in X86 directory.
llvm-svn: 144394
2011-11-11 18:10:38 +00:00
Dan Bailey
ad6c209a79 allow non-device function calls in PTX when natively handling device-side printf
llvm-svn: 144388
2011-11-11 14:45:12 +00:00
Craig Topper
50df7c3842 Add lowering for AVX2 shift instructions.
llvm-svn: 144380
2011-11-11 07:39:23 +00:00
Chad Rosier
feb72bfc08 Add support for using immediates with select instructions.
rdar://10412592

llvm-svn: 144376
2011-11-11 06:20:39 +00:00
Eli Friedman
285b451941 Make sure to expand SIGN_EXTEND_INREG for NEON vectors. PR11319, round 3.
llvm-svn: 144361
2011-11-11 03:16:38 +00:00
Eli Friedman
127d98ab35 Get rid of an optimization in SCCP which appears to have many issues. Specifically, it doesn't handle many cases involving undef correctly, and it is missing other checks which
lead to it trying to re-mark a value marked as a constant with a different value.  It also appears to trigger very rarely.

Fixes PR11357.

llvm-svn: 144352
2011-11-11 01:16:15 +00:00
Chad Rosier
ac92994773 Add support for using MVN to materialize negative constants.
rdar://10412592

llvm-svn: 144348
2011-11-11 00:36:21 +00:00
Jim Grosbach
bd7df609b7 Thumb2 parsing for push/pop w/ hi registers in the reglist.
rdar://10130228.

llvm-svn: 144331
2011-11-10 23:17:11 +00:00
Rafael Espindola
e7024f983a Check in getOrCreateSubprogramDIE if a declaration exists and if so output
it first.

This is a more general fix to pr11300.

llvm-svn: 144324
2011-11-10 22:34:29 +00:00
Jim Grosbach
c3651cb620 Thumb MUL assembly parsing for 3-operand form.
Get the source register that isn't tied to the destination register correct,
even when the assembly source operand order is backwards.

rdar://10428630

llvm-svn: 144322
2011-11-10 22:10:12 +00:00
Chad Rosier
7b7dced006 When in ARM mode, LDRH/STRH require special handling of negative offsets.
For correctness, disable this for now.
rdar://10418009

llvm-svn: 144316
2011-11-10 21:09:49 +00:00
Jim Grosbach
f5943e4c5e ARM assembly parsing for LSR/LSL/ROR(immediate).
More of rdar://9704684

llvm-svn: 144301
2011-11-10 19:18:01 +00:00
Jim Grosbach
b66dfc2999 ARM assembly parsing for ASR(immediate).
Start of rdar://9704684

llvm-svn: 144293
2011-11-10 16:44:55 +00:00
NAKAMURA Takumi
ea14fd81c6 test/CodeGen/X86/lsr-loop-exit-cond.ll: Try to appease linux and freebsd bots to specify explicit -mtriple=x86_64-darwin.
I guess it expects -relocation-model=pic.

llvm-svn: 144290
2011-11-10 14:18:59 +00:00
Evan Cheng
4760ff0763 Use a bigger hammer to fix PR11314 by disabling the "forcing two-address
instruction lower optimization" in the pre-RA scheduler.

The optimization, rather the hack, was done before MI use-list was available.
Now we should be able to implement it in a better way, perhaps in the
two-address pass until a MI scheduler is available.

Now that the scheduler has to backtrack to handle call sequences. Adding
artificial scheduling constraints is just not safe. Furthermore, the hack
is not taking all the other scheduling decisions into consideration so it's just
as likely to pessimize code. So I view disabling this optimization goodness
regardless of PR11314.

llvm-svn: 144267
2011-11-10 07:43:16 +00:00
Chad Rosier
69cdae5eb9 For immediate encodings of icmp, zero or sign extend first. Then
determine if the value is negative and flip the sign accordingly.
rdar://10422026

llvm-svn: 144258
2011-11-10 01:30:39 +00:00
Jakob Stoklund Olesen
bc48cd34b6 Strip old implicit operands after foldMemoryOperand.
The TII.foldMemoryOperand hook preserves implicit operands from the
original instruction.  This is not what we want when those implicit
operands refer to the register being spilled.

Implicit operands referring to other registers are preserved.

This fixes PR11347.

llvm-svn: 144247
2011-11-10 00:17:03 +00:00
Jim Grosbach
8591bd2bab Thumb2 assembly parsing STMDB w/ optional .w suffix.
rdar://10422955

llvm-svn: 144242
2011-11-09 23:44:23 +00:00
Eli Friedman
c93f8aa514 Make sure we correctly unroll conversions between v2f64 and v2i32 on ARM.
llvm-svn: 144241
2011-11-09 23:36:02 +00:00
Pete Cooper
38700a1201 DeadStoreElimination can now trim the size of a store if the end of the store is dead.
Currently checks alignment and killing stores on a power of 2 boundary as this is likely
to trim the size of the earlier store without breaking large vector stores into scalar ones.

Fixes <rdar://problem/10140300>

llvm-svn: 144239
2011-11-09 23:07:35 +00:00
Eli Friedman
b01f15653c Add check so we don't try to perform an impossible transformation. Fixes issue from PR11319.
llvm-svn: 144216
2011-11-09 22:25:12 +00:00
Nadav Rotem
ddc6bfa543 AVX2: Add patterns for variable shift operations
llvm-svn: 144212
2011-11-09 21:22:13 +00:00
Chad Rosier
228dc76221 Use REs to remove dependencies on the register allocation order.
llvm-svn: 144209
2011-11-09 20:06:13 +00:00
Duncan Sands
2934a0eaeb Speculatively revert commit 144124 (djg) in the hope that the 32 bit
dragonegg self-host buildbot will recover (it is complaining about object
files differing between different build stages).  Original commit message:

Add a hack to the scheduler to disable pseudo-two-address dependencies in
basic blocks containing calls. This works around a problem in which
these artificial dependencies can get tied up in calling seqeunce
scheduling in a way that makes the graph unschedulable with the current
approach of using artificial physical register dependencies for calling
sequences. This fixes PR11314.

llvm-svn: 144188
2011-11-09 14:20:48 +00:00
Nadav Rotem
e66a72a2c4 Add AVX2 support for vselect of v32i8
llvm-svn: 144187
2011-11-09 13:21:28 +00:00