Evan Cheng
1faccbd51a
Rename -pre-RA-sched=hybrid to -pre-RA-sched=list-hybrid.
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llvm-svn: 104306
2010-05-21 00:42:32 +00:00
Daniel Dunbar
8824824171
Remove dead option.
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llvm-svn: 104303
2010-05-21 00:27:55 +00:00
Devang Patel
765d605934
Simplify.
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llvm-svn: 104302
2010-05-21 00:10:20 +00:00
Daniel Dunbar
38460e2596
Fix __crashreport_info__ declaration.
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llvm-svn: 104300
2010-05-20 23:50:19 +00:00
Evan Cheng
b5de7de4ce
Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode.
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llvm-svn: 104293
2010-05-20 23:26:43 +00:00
Dan Gohman
3274120902
DominatorTree.getNode can return null for unreachable blocks.
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llvm-svn: 104290
2010-05-20 22:46:54 +00:00
Dan Gohman
b841e5c433
Minor code cleanups.
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llvm-svn: 104287
2010-05-20 22:25:20 +00:00
Mikhail Glushenkov
5ead1e50a7
Print a space after the colon.
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llvm-svn: 104279
2010-05-20 21:11:37 +00:00
Dan Gohman
06b35689ec
Make Solve check its own post-condition, to reduce clutter in the
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top-level LSRInstance logic.
llvm-svn: 104278
2010-05-20 20:59:23 +00:00
Dan Gohman
2702e3105d
Add comments.
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llvm-svn: 104276
2010-05-20 20:52:00 +00:00
Daniel Dunbar
3a0c98ca87
MC/X86: Add movq alias for movabsq, to allow matching 64-bit immediates with movq.
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llvm-svn: 104275
2010-05-20 20:36:29 +00:00
Devang Patel
3d4cd812aa
Rename variable. add comment.
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llvm-svn: 104274
2010-05-20 20:35:24 +00:00
Dan Gohman
5f16e1b2cb
More code cleanups. Use iterators instead of indices when indices
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aren't needed.
llvm-svn: 104273
2010-05-20 20:33:18 +00:00
Daniel Dunbar
030b1001c0
X86: Model i64i32imm properly, as a subclass of all immediates.
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llvm-svn: 104272
2010-05-20 20:20:39 +00:00
Daniel Dunbar
6cbde7d71e
X86: Fix immediate type of FOO64i32 operations.
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llvm-svn: 104271
2010-05-20 20:20:35 +00:00
Daniel Dunbar
64807873ec
tblgen/Target: Add a isAsmParserOnly bit, and teach the disassembler to honor
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it.
llvm-svn: 104270
2010-05-20 20:20:32 +00:00
Dan Gohman
aa116e0758
Fix OptimizeShadowIV to set Changed. Change OptimizeLoopTermCond to set
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Changed directly instead of using a return value.
Rename FilterOutUndesirableDedicatedRegisters's Changed variable to
distinguish it from LSRInstance's Changed member.
llvm-svn: 104269
2010-05-20 20:05:31 +00:00
Dan Gohman
ad77b290d0
Add some comments.
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llvm-svn: 104268
2010-05-20 20:00:41 +00:00
Dan Gohman
b08c4f5ab9
Simplify this code. Don't do a DomTreeNode lookup for each visited block.
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llvm-svn: 104267
2010-05-20 20:00:25 +00:00
Devang Patel
32a1ce3b3a
Refactor.
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llvm-svn: 104265
2010-05-20 19:57:06 +00:00
Matt Fleming
eb6f789e6f
Grammar fix. This is a test commit.
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llvm-svn: 104264
2010-05-20 19:45:09 +00:00
Dan Gohman
86f6190fc2
Minor code cleanups.
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llvm-svn: 104263
2010-05-20 19:44:23 +00:00
Dan Gohman
89f64e13fe
When canonicalizing icmp operand order to put the loop invariant
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operand on the left, the interesting operand is on the right. This
fixes a bug where LSR was failing to recognize ICmpZero uses,
which led it to be unable to reverse the induction variable in the
attached testcase.
Delete test/CodeGen/X86/stack-color-with-reg-2.ll, because its test
is extremely fragile and hard to meaningfully update.
llvm-svn: 104262
2010-05-20 19:26:52 +00:00
Mikhail Glushenkov
ed1c9f41bf
llvmc: Make segfault detection work on Win32.
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llvm-svn: 104261
2010-05-20 19:23:47 +00:00
Dan Gohman
75ee6c3611
Set Changed to true when canonicalizing ICmp operand order; even though
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it isn't a very interesting change, it's a change nonetheless.
llvm-svn: 104260
2010-05-20 19:16:03 +00:00
Bob Wilson
11aebf39f1
Handle Neon v2f64 and v2i64 vector shuffles as register copies.
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This fixes the remaining issue with pr7167.
llvm-svn: 104257
2010-05-20 18:39:53 +00:00
Jim Grosbach
5029c599b3
Remove dbg_value workaround and associated command line option
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llvm-svn: 104254
2010-05-20 18:34:01 +00:00
Dan Gohman
7dcd59b8b2
Delete MMX_MOVQ64gmr. It was the same as MMX_MOVQ64mr, but it didn't
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have a pattern and it had an invalid encoding.
llvm-svn: 104244
2010-05-20 18:05:01 +00:00
Dale Johannesen
78714b5dc9
The PPC MFCR instruction implicitly uses all 8 of the CR
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registers. Currently it is not so marked, which leads to
VCMPEQ instructions that feed into it getting deleted.
If it is so marked, local RA complains about this sequence:
vreg = MCRF CR0
MFCR <kill of whatever preg got assigned to vreg>
All current uses of this instruction are only interested in
one of the 8 CR registers, so redefine MFCR to be a normal
unary instruction with a CR input (which is emitted only as
a comment). That avoids all problems. 7739628.
llvm-svn: 104238
2010-05-20 17:48:26 +00:00
Devang Patel
ae24244a10
Strip llvm.dbg.lv also.
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llvm-svn: 104236
2010-05-20 16:49:22 +00:00
Dan Gohman
af66103d32
Rename a variable to avoid shadowing.
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llvm-svn: 104234
2010-05-20 16:41:11 +00:00
Devang Patel
f90f78669f
Split DbgVariable. Eventually, variable info will be communicated through frame index, or DBG_VALUE instruction, or collection of DBG_VALUE instructions. Plus each DbgVariable may not need a label.
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llvm-svn: 104233
2010-05-20 16:36:41 +00:00
Dan Gohman
db5be4dfc7
Minor code simplification.
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llvm-svn: 104232
2010-05-20 16:23:28 +00:00
Dan Gohman
c8b4555a94
Fix assembly parsing and encoding of the pushf and popf family of
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instructions.
llvm-svn: 104231
2010-05-20 16:16:00 +00:00
Dan Gohman
80d2fc54e9
Set neverHasSideEffects on 64-bit pushf and popf, for consistency with
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16-bit and 32-bit pushf and popf.
llvm-svn: 104228
2010-05-20 15:42:55 +00:00
Dan Gohman
139527105c
Move the code for deleting BaseRegs and LSRUses into helper functions,
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and fix a bug that valgrind noticed where the code would std::swap an
element with itself.
llvm-svn: 104225
2010-05-20 15:17:54 +00:00
Benjamin Kramer
47bf53a5dd
Reduce string trashing.
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llvm-svn: 104223
2010-05-20 14:14:22 +00:00
Evan Cheng
0d88ad2de1
Add a hybrid bottom up scheduler that reduce register usage while avoiding
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pipeline stall. It's useful for targets like ARM cortex-a8. NEON has a lot
of long latency instructions so a strict register pressure reduction
scheduler does not work well.
Early experiments show this speeds up some NEON loops by over 30%.
llvm-svn: 104216
2010-05-20 06:13:19 +00:00
Nick Lewycky
8d3f839753
Fix typo in comment.
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llvm-svn: 104209
2010-05-20 03:30:09 +00:00
Dan Gohman
52dcd5fb9a
Define the x86 pause instruction.
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llvm-svn: 104204
2010-05-20 01:35:50 +00:00
Dan Gohman
00b8752500
Fix the sfence instruction to use MRM_F8 instead of MRM7r, since it
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doesn't have a register operand. Also, use I instead of PSI, for
consistency with mfence and lfence.
llvm-svn: 104203
2010-05-20 01:23:41 +00:00
Eric Christopher
09658d704d
Fix build by actually declaring the variable.
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llvm-svn: 104201
2010-05-20 00:59:30 +00:00
Eric Christopher
1a7bc06b28
Partial code for emitting thread local bss data.
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llvm-svn: 104197
2010-05-20 00:49:07 +00:00
Bill Wendling
e7a42798bc
Match "4" or "8" depending upon if it's 32- or 64-bit.
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llvm-svn: 104196
2010-05-20 00:27:10 +00:00
Eric Christopher
1643e2f4c6
Once more, with feeling.
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llvm-svn: 104190
2010-05-20 00:07:13 +00:00
Daniel Dunbar
1c27a3b79d
lit: Add another place to look for bash.
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llvm-svn: 104189
2010-05-19 23:56:09 +00:00
Dan Gohman
772b731ca5
Teach LSR how to cope better with unrolled loops on targets where
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the addressing modes don't make this trivially easy. This allows
it to avoid falling into the less precise heuristics in more
cases.
llvm-svn: 104186
2010-05-19 23:43:12 +00:00
Bob Wilson
2dbe0d9886
Optimize away insertelement of an undef value. This shows up in
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test/Codegen/ARM/reg_sequence.ll but it doesn't affect the generated code
because the coalescer cleans it up. Radar 7998853.
llvm-svn: 104185
2010-05-19 23:42:58 +00:00
Chris Lattner
aedd148163
fix rdar://7986634 - match instruction opcodes case insensitively.
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llvm-svn: 104183
2010-05-19 23:34:33 +00:00
Bill Wendling
483ce4b9b7
Testcase for r104181.
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llvm-svn: 104182
2010-05-19 23:33:26 +00:00