RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-04-05 17:21:39 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity
34,775 Commits 6 Branches 6 Tags
Commit Graph

156 Commits

Author SHA1 Message Date
Evan Cheng
d11cd4a095 EXTRACT_SUBREG coalescing support. The coalescer now treats EXTRACT_SUBREG like 
(almost) a register copy. However, it always coalesced to the register of the
RHS (the super-register). All uses of the result of a EXTRACT_SUBREG are sub-
register uses which adds subtle complications to load folding, spiller rewrite,
etc.

llvm-svn: 42899
 2007-10-12 08:50:34 +00:00
Dan Gohman
fb60c0dfed Remove isReg, isImm, and isMBB, and change all their users to use 
isRegister, isImmediate, and isMachineBasicBlock, which are equivalent,
and more popular.

llvm-svn: 41958
 2007-09-14 20:33:02 +00:00
Dan Gohman
53119779c2 Remove spurious consts. This fixes warnings with compilers that 
are strict about such things.

llvm-svn: 41956
 2007-09-14 20:08:19 +00:00
Christopher Lamb
cb63a77a51 Remove subreg index from MachineInstr's and also keep vregs as unsigned when adding operands. 
llvm-svn: 40514
 2007-07-26 07:00:46 +00:00
Evan Cheng
88c463eb8c MachineInstr::isPredicable() is no longer needed. 
llvm-svn: 37599
 2007-06-15 19:06:07 +00:00
Evan Cheng
d8b25a2091 Add missing const qualifiers. 
llvm-svn: 37341
 2007-05-29 18:35:22 +00:00
Evan Cheng
6f761adecb Rename M_PREDICATED to M_PREDICABLE; Moved isPredicable() to MachineInstr. 
llvm-svn: 37121
 2007-05-16 20:56:08 +00:00
Evan Cheng
eea85a767e Added getNumExplicitOperands and findFirstPredOperand. 
llvm-svn: 37064
 2007-05-15 01:26:09 +00:00
Nate Begeman
767ee95d29 llvm bug #1350, parts 1, 2, and 3. 
llvm-svn: 36618
 2007-05-01 05:57:02 +00:00
Evan Cheng
eff332e3e1 Rename findRegisterUseOperand to findRegisterUseOperandIdx to avoid confusion. 
llvm-svn: 36483
 2007-04-26 19:00:32 +00:00
Evan Cheng
201771637e Change findRegisterUseOperand() to return operand index instead. 
llvm-svn: 35363
 2007-03-26 22:37:45 +00:00
Evan Cheng
387f1c2bdf Use findRegisterUseOperand to find a kill of particular register. 
llvm-svn: 34512
 2007-02-23 01:04:26 +00:00
Evan Cheng
e4ab9c032b Re-apply my liveintervalanalysis changes. Now with PR1207 fixes. 
llvm-svn: 34428
 2007-02-19 21:49:54 +00:00
Reid Spencer
b27fcf3482 For PR1207: 
Revert patches that caused the problem. Evan, please investigate and reapply
when you've discovered the problem.

llvm-svn: 34399
 2007-02-19 03:20:00 +00:00
Evan Cheng
35f59a6dd2 Added findRegisterDefOperand(). 
llvm-svn: 34380
 2007-02-17 11:10:18 +00:00
Evan Cheng
5b8b96e9de Print <dead> def operands. 
llvm-svn: 34343
 2007-02-16 09:49:18 +00:00
Jeff Cohen
c396e18e8e The best unbreakage yet, addressing Bill's concerns. 
llvm-svn: 32622
 2006-12-16 02:15:42 +00:00
Jeff Cohen
03161dd132 An even better unbreakage... 
llvm-svn: 32617
 2006-12-15 22:57:14 +00:00
Bill Wendling
a3246c4272 Changed llvm_ostream et all to OStream. llvm_cerr, llvm_cout, llvm_null, are 
now cerr, cout, and NullStream resp.

llvm-svn: 32298
 2006-12-07 01:30:32 +00:00
Evan Cheng
59494f9e3d Move copyKillDeadInfo out-of-line. Add findRegisterUseOperand(). 
llvm-svn: 32273
 2006-12-06 08:27:42 +00:00
Evan Cheng
cb65ba1821 - MachineInstr now keeps a ptr to TargetInstrDescriptor instead of Opcode. 
- Remove the ugly TargetInstrDescriptors hack.

llvm-svn: 32032
 2006-11-30 07:08:44 +00:00
Bill Wendling
d8c0883f20 Use llvm streams instead of <iostream> 
llvm-svn: 31985
 2006-11-28 22:48:48 +00:00
Evan Cheng
e176869ec0 Clean up. 
llvm-svn: 31957
 2006-11-28 02:25:34 +00:00
Evan Cheng
98fa7ab4d7 Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead 
of opcode and number of operands.

llvm-svn: 31947
 2006-11-27 23:37:22 +00:00
Chris Lattner
31f45746ad setOperand should not zap the operand list or add implicit operands to an 
instruction.  Doing so breaks the FP stackifier, the alpha branch selector
the sparc fpmover.

This fixes PR1012 and CodeGen/X86/fp-stack-compare.ll

llvm-svn: 31876
 2006-11-20 17:57:22 +00:00
Evan Cheng
cf45b9fa95 Minor updates. 
llvm-svn: 31761
 2006-11-15 20:54:29 +00:00
Evan Cheng
7cabf9d02c - Let MachineInstr ctors add implicit def and use operands. Other operands 
will be inserted before these operands. If the opcode changes (by
  setOpcode), the implicit operands are updated as well.
- Added IsKill, IsDead fields to MachineOperand in preparation for changes
  that move kill / dead info to MachineInstr's.

llvm-svn: 31711
 2006-11-13 23:34:06 +00:00
Evan Cheng
7dab9abfb8 Add methods to add implicit def use operands to a MI. 
llvm-svn: 31675
 2006-11-11 10:20:02 +00:00
Evan Cheng
013597778d Add implicit def / use operands to MachineInstr. 
llvm-svn: 31633
 2006-11-10 08:43:01 +00:00
Chris Lattner
5bb7f41bca be more aggressive about matching identical instructions. 
llvm-svn: 31179
 2006-10-25 18:08:14 +00:00
Chris Lattner
cf4137d0b9 implement MachineOperand::isIdenticalTo 
llvm-svn: 31088
 2006-10-20 22:39:59 +00:00
Chris Lattner
0fad1515ee Only call isUse/isDef on register operands 
llvm-svn: 30118
 2006-09-05 20:19:27 +00:00
Evan Cheng
07d8ccec50 Instructions with variable operands (variable_ops) can have a number required 
operands. e.g.
def CALL32r : I<0xFF, MRM2r, (ops GR32:$dst, variable_ops),
                "call {*}$dst", [(X86call GR32:$dst)]>;
TableGen should emit operand informations for the "required" operands.

Added a target instruction info flag M_VARIABLE_OPS to indicate the target
instruction may have more operands in addition to the minimum required
operands.

llvm-svn: 28791
 2006-06-15 07:22:16 +00:00
Evan Cheng
328b47bc28 Remove a bogus cast. 
llvm-svn: 28492
 2006-05-26 08:00:14 +00:00
Chris Lattner
db888e7880 Final pass of minor cleanups for MachineInstr 
llvm-svn: 28110
 2006-05-04 19:36:09 +00:00
Chris Lattner
32adc4592f Remove redundancy and a level of indirection when creating machine operands 
llvm-svn: 28107
 2006-05-04 19:14:44 +00:00
Chris Lattner
075404adaa Remove and simplify some more machineinstr/machineoperand stuff. 
llvm-svn: 28105
 2006-05-04 18:16:01 +00:00
Chris Lattner
eb41c99161 Rename MO_VirtualRegister -> MO_Register. Clean up immediate handling. 
llvm-svn: 28104
 2006-05-04 18:05:43 +00:00
Chris Lattner
685568510a Move some methods out of MachineInstr into MachineOperand 
llvm-svn: 28102
 2006-05-04 17:52:23 +00:00
Chris Lattner
97f1af2f14 There shalt be only one "immediate" operand type! 
llvm-svn: 28099
 2006-05-04 17:21:20 +00:00
Chris Lattner
51b0cac238 Change "value" in MachineOperand to be a GlobalValue, as that is the only 
thing that can be in it.  Remove a dead method.

llvm-svn: 28098
 2006-05-04 17:02:51 +00:00
Chris Lattner
a39a7f900f Remove a bunch more dead V9 specific stuff 
llvm-svn: 28094
 2006-05-04 01:26:39 +00:00
Chris Lattner
c779fca289 Remove a bunch more SparcV9 specific stuff 
llvm-svn: 28093
 2006-05-04 01:15:02 +00:00
Chris Lattner
ed58ec2a57 Remove some more V9-specific stuff. 
llvm-svn: 28092
 2006-05-04 00:49:59 +00:00
Chris Lattner
0f89e6b11d Remove some more unused stuff from MachineInstr that was leftover from V9. 
llvm-svn: 28091
 2006-05-04 00:44:25 +00:00
Nate Begeman
7ed816f900 JumpTable support! What this represents is working asm and jit support for 
x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.

llvm-svn: 27947
 2006-04-22 18:53:45 +00:00
Chris Lattner
04a8496ef0 This field no longer exists 
llvm-svn: 27899
 2006-04-20 18:32:41 +00:00
Chris Lattner
a6a6ac15af Remove some of the obvious V9-specific cruft 
llvm-svn: 27893
 2006-04-20 18:08:53 +00:00
Chris Lattner
5f5a9cc8ea Add a MachineInstr::eraseFromParent convenience method. 
llvm-svn: 27775
 2006-04-17 21:35:41 +00:00
Misha Brukman
774e55c446 Remove trailing whitespace 
llvm-svn: 21420
 2005-04-21 22:36:52 +00:00