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10556 Commits

Author SHA1 Message Date
Daniel Dunbar
9ced206b3a MC/ELF: Allow null values in virtual sections, ELF doesn't use special 
directives for putting contents in .bss, for example.

llvm-svn: 111376
 2010-08-18 18:22:37 +00:00
Kalle Raiskila
05d3cc2ef8 Fix a bug with insertelement on SPU. 
The previous algorithm in LowerVECTOR_SHUFFLE 
didn't check all requirements for "monotonic" shuffles.

llvm-svn: 111361
 2010-08-18 10:20:29 +00:00
Kalle Raiskila
8b6f5df4ae Remove all traces of v2[i,f]32 on SPU. 
The "half vectors" are now widened to full size by the legalizer.
The only exception is in parameter passing, where half vectors are 
expanded. This causes changes to some dejagnu tests.

llvm-svn: 111360
 2010-08-18 10:04:39 +00:00
Kalle Raiskila
0ee13a45c8 Change SPU C calling convention to match that described in 
"SPU Application Binary Interface Specification, v1.9" by
IBM. 
Specifically: use r3-r74 to pass parameters and the return value.

llvm-svn: 111358
 2010-08-18 09:50:30 +00:00
Chris Lattner
b4602679d7 fix a buggy test 
llvm-svn: 111354
 2010-08-18 04:55:12 +00:00
Chris Lattner
49d0f29752 fix PR7589: In brief: 
gep P, (zext x) != gep P, (sext x)

DecomposeGEPExpression was getting this wrong, confusing
basicaa.

llvm-svn: 111352
 2010-08-18 04:28:19 +00:00
Chris Lattner
6ac971a27f filecheckize and detrivialize. 
llvm-svn: 111350
 2010-08-18 04:25:43 +00:00
Chris Lattner
ab876b6ce8 Fix PR7755: knowing something about an inval for a pred 
from the LHS should disable reconsidering that pred on the
RHS.  However, knowing something about the pred on the RHS
shouldn't disable subsequent additions on the RHS from
happening.

llvm-svn: 111349
 2010-08-18 03:14:36 +00:00
Bob Wilson
412be3eea6 Expand ZERO_EXTEND operations for NEON vector types. 
Testcase from Nick Lewycky.

llvm-svn: 111341
 2010-08-18 01:45:52 +00:00
Eric Christopher
08e9f0250a Temporarily revert r110987 as it's causing some miscompares in 
vector heavy code.  I'll re-enable when we've tracked down the problem.

llvm-svn: 111318
 2010-08-17 22:55:27 +00:00
Dan Gohman
ee89338e37 Tweak IVUsers' concept of "interesting" to exclude add recurrences 
where the step value is an induction variable from an outer loop, to
avoid trouble trying to re-expand such expressions. This effectively
hides such expressions from indvars and lsr, which prevents them
from getting into trouble.

llvm-svn: 111317
 2010-08-17 22:50:37 +00:00
Evan Cheng
d6348fe9b2 Add nounwind. 
llvm-svn: 111312
 2010-08-17 22:35:20 +00:00
Dale Johannesen
535ca58e85 Make fast scheduler handle asm clobbers correctly. 
PR 7882.  Follows suggestion by Amaury Pouly, thanks.

llvm-svn: 111306
 2010-08-17 22:17:24 +00:00
Anton Korobeynikov
8c6bfd1c24 Add some win64 coff goodness. 
Patch by Cameron Esfahani!

llvm-svn: 111287
 2010-08-17 21:05:54 +00:00
Dan Gohman
e26025ddd0 When rotating loops, put the original header at the bottom of the 
loop, making the resulting loop significantly less ugly.  Also, zap
its trivial PHI nodes, since it's easy.

llvm-svn: 111255
 2010-08-17 17:39:21 +00:00
Bob Wilson
e382fce916 Change ARM PKHTB and PKHBT instructions to use a shift_imm operand to avoid 
printing "lsl #0".  This fixes the remaining parts of pr7792.  Make
corresponding changes for encoding/decoding these instructions.

llvm-svn: 111251
 2010-08-17 17:23:19 +00:00
Bob Wilson
6239dc42c6 Allow more cases of undef shuffle indices and add tests for them. 
llvm-svn: 111226
 2010-08-17 05:54:34 +00:00
Evan Cheng
0163d059e4 PHI elimination should not break back edge. It can cause some significant code placement issues. rdar://8263994 
good:
LBB0_2:
  mov     r2, r0
  . . .
  mov     r1, r2
  bne     LBB0_2

bad:
LBB0_2:
  mov     r2, r0
  . . .
@ BB#3:
  mov     r1, r2
  b       LBB0_2

llvm-svn: 111221
 2010-08-17 01:20:36 +00:00
Bob Wilson
2c5e6a9214 Add a testcase for svn 111208. 
llvm-svn: 111212
 2010-08-16 23:44:29 +00:00
Bob Wilson
d662e8cd02 Generalize a pattern for PKHTB: an SRL of 16-31 bits will guarantee 
that the high halfword is zero.  The shift need not be exactly 16 bits.

llvm-svn: 111196
 2010-08-16 22:26:55 +00:00
Bob Wilson
b776a55df5 Convert test to FileCheck. 
llvm-svn: 111195
 2010-08-16 22:21:13 +00:00
Bob Wilson
f174416619 Convert a test to use FileCheck. 
llvm-svn: 111153
 2010-08-16 17:05:27 +00:00
Dan Gohman
9178d0792f Instead, teach SimplifyCFG to trim non-address-taken blocks from 
indirectbr destination lists.

llvm-svn: 111122
 2010-08-16 14:41:14 +00:00
Dan Gohman
8ed4d1646e Revert r111058, the lint check for indirectbr successors that aren't 
address-taken. This can occur normally, if the code which took the
address got DCEd.

llvm-svn: 111121
 2010-08-16 14:39:19 +00:00
Benjamin Kramer
0224854fdc Test expects SSE, give him SSE. 
llvm-svn: 111115
 2010-08-15 23:32:03 +00:00
Benjamin Kramer
3116e6f58d Restore arch on these test, they fail on arm. 
llvm-svn: 111109
 2010-08-15 20:42:56 +00:00
Dale Johannesen
6e5cf0f5b6 Mark as XFAIL on darwin 8. PR 7886. 
llvm-svn: 111108
 2010-08-15 19:40:29 +00:00
Mikhail Glushenkov
de1e03e890 Update tests. 
llvm-svn: 111096
 2010-08-15 07:07:24 +00:00
Dan Gohman
afb3db46d2 LoopSimplify shouldn't split loop backedges that use indirectbr. PR7867. 
llvm-svn: 111061
 2010-08-14 00:43:09 +00:00
Dan Gohman
d04a608a73 Teach SimplifyCFG how to simplify indirectbr instructions. 
- Eliminate redundant successors.
 - Convert an indirectbr with one successor into a direct branch.

Also, generalize SimplifyCFG to be able to be run on a function entry block.
It knows quite a few simplifications which are applicable to the entry
block, and it only needs a few checks to avoid trouble with the entry block.

llvm-svn: 111060
 2010-08-14 00:29:42 +00:00
Dan Gohman
422c164d8d Add a lint check for an indirectbr destination which has not 
had its address taken.

llvm-svn: 111058
 2010-08-13 23:56:28 +00:00
Bob Wilson
92bf5a7425 Add a Thumb2 t2RSBrr instruction for disassembly only. 
This fixes another part of PR7792.

llvm-svn: 111057
 2010-08-13 23:24:25 +00:00
Bob Wilson
ca672ee828 Temporarily disable tail calls on ARM to work around some linker problems. 
llvm-svn: 111050
 2010-08-13 22:43:33 +00:00
Bob Wilson
0883c6aae3 Move the Thumb2 SSAT and USAT optional shift operator out of the 
instruction opcode.  This fixes part of PR7792.

llvm-svn: 111047
 2010-08-13 21:48:10 +00:00
Dale Johannesen
3f9c148d0e Revert 110491. While not wrong, it was based on a 
misanalysis and is undesirable.

llvm-svn: 111028
 2010-08-13 18:43:45 +00:00
Mikhail Glushenkov
003526ceac One more XFAIL. 
llvm-svn: 111010
 2010-08-13 07:03:56 +00:00
Mikhail Glushenkov
0728ed703a More XFAILs. 
llvm-svn: 111008
 2010-08-13 07:01:55 +00:00
Mikhail Glushenkov
104be4cd20 Add an XFAIL. 
llvm-svn: 111004
 2010-08-13 04:15:45 +00:00
Mikhail Glushenkov
74fa906ef0 Remove -fexceptions from llvmc tests. 
llvm-svn: 110999
 2010-08-13 02:29:35 +00:00
Mikhail Glushenkov
d4d9dbc382 llvmc: fix two tests, remove XFAILs. 
Tested on Linux and Darwin; please add platform-specific XFAILs/mail me a bug
report if this still fails.

llvm-svn: 110998
 2010-08-13 02:29:24 +00:00
Nate Begeman
e57074fc48 Reapply this transformation now that it is passing the external test which it previously failed. 
llvm-svn: 110987
 2010-08-13 00:17:53 +00:00
Chris Lattner
fd40059e71 fix PR7876: If ipsccp decides that a function's address is taken 
before it rewrites the code, we need to use that in the post-rewrite pass.

llvm-svn: 110962
 2010-08-12 22:25:23 +00:00
Johnny Chen
78345b1dfe Cleaned up the for-disassembly-only entries in the arm instruction table so that 
the memory barrier variants (other than 'SY' full system domain read and write)
are treated as one instruction with option operand.

llvm-svn: 110951
 2010-08-12 20:46:17 +00:00
Bruno Cardoso Lopes
7cb26cb8be - Teach SSEDomainFix to switch between different levels of AVX instructions. Here we guess that AVX will have domain issues, so just implement them for consistency and in the future we remove if it's unnecessary. 
- Make foldMemoryOperandImpl aware of 256-bit zero vectors folding and support the 128-bit counterparts of AVX too.
- Make sure MOV[AU]PS instructions are only selected when SSE1 is enabled, and duplicate the patterns to match AVX.
- Add a testcase for a simple 128-bit zero vector creation.

llvm-svn: 110946
 2010-08-12 20:20:53 +00:00
Bob Wilson
c6c469889b Add a test for llvm-gcc svn 110632. 
llvm-svn: 110935
 2010-08-12 17:31:41 +00:00
Eric Christopher
34acdf57df Temporarily revert 110737 and 110734, they were causing failures 
in an external testsuite.

llvm-svn: 110905
 2010-08-12 07:01:22 +00:00
Bruno Cardoso Lopes
bb491bd56c Begin to support some vector operations for AVX 256-bit intructions. The long 
term goal here is to be able to match enough of vector_shuffle and build_vector
so all avx intrinsics which aren't mapped to their own built-ins but to
shufflevector calls can be codegen'd. This is the first (baby) step, support
building zeroed vectors.

llvm-svn: 110897
 2010-08-12 02:06:36 +00:00
Johnny Chen
fef1367b50 The autogened decoder was confusing the ARM STRBT for ARM USAT, because the .td 
entry for ARM STRBT is actually a super-instruction for A8.6.199 STRBT A1 & A2.
Recover by looking for ARM:USAT encoding pattern before delegating to the auto-
gened decoder.

Added a "usat" test case to arm-tests.txt.

llvm-svn: 110894
 2010-08-12 01:40:54 +00:00
Daniel Dunbar
4f45de1b1e MC/X86/AsmParser: Give an explicit error message when we reject an instruction 
because it could have an ambiguous suffix.

llvm-svn: 110890
 2010-08-12 00:55:42 +00:00
Devang Patel
66fc7d88ae This is x86 only test. 
llvm-svn: 110887
 2010-08-12 00:17:38 +00:00