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39752 Commits

Author SHA1 Message Date
Gabor Greif
6184b1a2fa cache result of operator* 
llvm-svn: 107976
 2010-07-09 15:40:10 +00:00
Gabor Greif
4d54dede01 cache result of operator* 
llvm-svn: 107975
 2010-07-09 15:25:42 +00:00
Gabor Greif
dcaa85787c cache result of operator* 
llvm-svn: 107974
 2010-07-09 15:25:09 +00:00
Gabor Greif
72d36e30a0 cache result of operator* 
llvm-svn: 107972
 2010-07-09 15:01:36 +00:00
Gabor Greif
00ab305f37 cache result of operator* (found by inspection) 
llvm-svn: 107971
 2010-07-09 14:48:08 +00:00
Gabor Greif
9ac508494f cache result of operator* 
llvm-svn: 107969
 2010-07-09 14:36:49 +00:00
Gabor Greif
a9fbbe2dbb cache result of operator* 
llvm-svn: 107968
 2010-07-09 14:29:14 +00:00
Gabor Greif
6c80602356 cache result of operator* 
llvm-svn: 107967
 2010-07-09 14:28:41 +00:00
Gabor Greif
a5fdd0955d cache result of operator* 
llvm-svn: 107966
 2010-07-09 14:18:23 +00:00
Gabor Greif
cda479a708 cache operator*'s result (in multiple functions) 
llvm-svn: 107965
 2010-07-09 14:02:13 +00:00
Gabor Greif
7bc80c7586 do not repeatedly dereference use_iterator 
llvm-svn: 107963
 2010-07-09 13:17:13 +00:00
Gabor Greif
9e2aa5d5d7 do not repeatedly dereference use_iterator 
llvm-svn: 107962
 2010-07-09 12:23:50 +00:00
Jakob Stoklund Olesen
e0dcc33889 Avoid creating %physreg:subidx operands in SimpleRegisterCoalescing::RemoveCopyByCommutingDef. 
This fixes PR7602.

llvm-svn: 107957
 2010-07-09 05:56:21 +00:00
Jakob Stoklund Olesen
2be8142157 Deal with a few remaining spots that assume physical registers have live intervals. 
This fixes PR7601.

llvm-svn: 107955
 2010-07-09 04:35:38 +00:00
Bruno Cardoso Lopes
144923dccf Merge VEX enums with other x86 enum forms. Also fix all checks of which VEX 
fields to use. 

llvm-svn: 107952
 2010-07-09 01:56:45 +00:00
Jakob Stoklund Olesen
daef6696d5 Fix broken isCopy handling in TrimLiveIntervalToLastUse. 
llvm-svn: 107950
 2010-07-09 01:27:21 +00:00
Jakob Stoklund Olesen
7824ff3af8 Handle COPY in VirtRegRewriter. 
llvm-svn: 107949
 2010-07-09 01:27:19 +00:00
Dan Gohman
dad9d461c3 Fix the memoperand offsets in code generated for va_start. 
llvm-svn: 107948
 2010-07-09 01:06:48 +00:00
Chris Lattner
a5c1c795a2 have the mc lowering process handle a few tail call forms, lowering them to 
jumps where possible and turning the TAILCALL marker in the instruction
asm string into a proper comment.

This eliminates a FIXME and is on the path to finishing:
rdar://7639610 - eliminate encoding and asm info for TAILJMPd TAILJMPr TAILJMPn, etc.

However, I can't eliminate the encodings for these instructions because the JIT
still exists and has its own copy of the encoder, sigh.

llvm-svn: 107946
 2010-07-09 00:49:41 +00:00
Bob Wilson
f15e542bdc Print "dregpair" NEON operands with a space between them, for readability and 
consistency with other instructions that have lists of register operands.

llvm-svn: 107944
 2010-07-09 00:47:20 +00:00
Dan Gohman
7e6e4dd058 Re-apply bottom-up fast-isel, with fixes. Be very careful to avoid emitting 
a DBG_VALUE after a terminator, or emitting any instructions before an EH_LABEL.

llvm-svn: 107943
 2010-07-09 00:39:23 +00:00
Bruno Cardoso Lopes
a6bfda61b9 Factor out x86 segment override prefix encoding, and also use it for VEX 
llvm-svn: 107942
 2010-07-09 00:38:14 +00:00
Bob Wilson
dd02fe62a2 Reenable DAG combining for vector shuffles. It looks like it was temporarily 
disabled and then never turned back on again.  Adjust some tests, one because
this change avoids an unnecessary instruction, and the other to make it
continue testing what it was intended to test.

llvm-svn: 107941
 2010-07-09 00:38:12 +00:00
Chris Lattner
fe434abafa reject pseudo instructions early in the encoder. 
llvm-svn: 107939
 2010-07-09 00:17:50 +00:00
Bruno Cardoso Lopes
f00a155876 Remove trailing whitespaces from file 
llvm-svn: 107937
 2010-07-09 00:07:19 +00:00
Chris Lattner
49ac65543c Change LEA to have 5 operands for its memory operand, just 
like all other instructions, even though a segment is not
allowed.  This resolves a bunch of gross hacks in the 
encoder and makes LEA more consistent with the rest of the
instruction set.

No functionality change.

llvm-svn: 107934
 2010-07-08 23:46:44 +00:00
Stuart Hastings
a3999081cf Reverting r107918 and r107919. Radar 8063111. 
llvm-svn: 107930
 2010-07-08 23:25:39 +00:00
Jakob Stoklund Olesen
099946a71b Revert "Fix broken isCopy handling in TrimLiveIntervalToLastUse" 
This reverts commit 107921. It broke the clang self host.

llvm-svn: 107926
 2010-07-08 22:52:47 +00:00
Chris Lattner
18802e1a55 add some long-overdue enums to refer to the parts of the 5-operand 
X86 memory operand.

llvm-svn: 107925
 2010-07-08 22:41:28 +00:00
Devang Patel
2abdcdfb40 Relax assertion. In optimized code, it is possible that first instruction is coming from a inlined function. 
This fixes PR7596 .

llvm-svn: 107923
 2010-07-08 22:39:20 +00:00
Bill Wendling
8f0fcd1623 Extension of r107506. Make sure that we don't mark a function as having a call 
if the inline ASM doesn't need a stack frame.

llvm-svn: 107922
 2010-07-08 22:38:02 +00:00
Jakob Stoklund Olesen
1ecf890d62 Fix broken isCopy handling in TrimLiveIntervalToLastUse 
llvm-svn: 107921
 2010-07-08 22:30:38 +00:00
Jakob Stoklund Olesen
1ae7342eaf Remember the VR64 register class 
llvm-svn: 107920
 2010-07-08 22:30:35 +00:00
Stuart Hastings
b70d4e06e3 Fix decl/def debug info for template functions. Radar 8063111. 
llvm-svn: 107919
 2010-07-08 22:28:59 +00:00
Chris Lattner
012d7537ee Rework segment prefix emission code to handle segments 
in memory operands at the same type as hard coded segments.
This fixes problems where we'd emit the segment override after
the REX prefix on instructions like:
mov %gs:(%rdi), %rax

This fixes rdar://8127102.  I have several cleanup patches coming
next.

llvm-svn: 107917
 2010-07-08 22:28:12 +00:00
Chris Lattner
660851a040 introduce a new X86II::getMemoryOperandNo method, which 
returns the start of the memory operand for an instruction.

Introduce a new "X86AddrSegment" enum to reduce # magic numbers
referring to X86 memory operand layout.

llvm-svn: 107916
 2010-07-08 22:27:06 +00:00
Kalle Raiskila
725a1a4ad2 Switch SPU calling convention (function arguments) 
to a Tablegen implementation.

llvm-svn: 107913
 2010-07-08 21:15:22 +00:00
Kevin Enderby
8a8d96b89c Revert some unneeded parts of the change in r107886 for the 
.weak_def_can_be_hidden directive.  Chris pointed out that the MCAsmInfo.h/.cpp
chunks aren't needed for this until the compiler starts generating these.  And
when that happens it will be more convenient for it to be a bool than a const
char*.

llvm-svn: 107906
 2010-07-08 20:30:44 +00:00
Evan Cheng
5307ec12d7 Check for FiniteOnlyFPMath as well. 
llvm-svn: 107904
 2010-07-08 20:12:24 +00:00
Devang Patel
69b391b5b1 Reuse DIEInteger for 1. This is frequently used while emitting an attribute using dwarf::DW_FORM_flag form. 
llvm-svn: 107903
 2010-07-08 20:10:35 +00:00
Jakob Stoklund Olesen
f9441b5025 Teach the x86 floating point stackifier to handle COPY instructions. 
This pass runs before COPY instructions are passed to copyPhysReg, so we simply
translate COPY to the proper pseudo instruction. Note that copyPhysReg does not
handle floating point stack copies.

Once COPY is used everywhere, this can be cleaned up a bit, and most of the
pseudo instructions can be removed.

llvm-svn: 107899
 2010-07-08 19:46:30 +00:00
Jakob Stoklund Olesen
aed86b1af7 Implement X86InstrInfo::copyPhysReg 
llvm-svn: 107898
 2010-07-08 19:46:25 +00:00
Bob Wilson
12922e6bec The NEONPreAllocPass should never have to assign fixed registers anymore. 
This pass can go away entirely soon.

llvm-svn: 107892
 2010-07-08 17:45:26 +00:00
Bob Wilson
fca7a252fb For big-endian systems, VLD2/VST2 with 32-bit vector elements will swap the 
words within the 64-bit D registers.  Use VLD1/VST1 with 64-bit elements
instead.

llvm-svn: 107890
 2010-07-08 17:44:00 +00:00
Kevin Enderby
9bf8ee521c Added the darwin .weak_def_can_be_hidden directive. 
llvm-svn: 107886
 2010-07-08 17:22:42 +00:00
Bob Wilson
b07d97d333 Clean up a comment. 
llvm-svn: 107882
 2010-07-08 16:54:45 +00:00
Jim Grosbach
38aae4a067 Clean up scavengeRegister() a bit to prefer available regs, which allows 
the simplification of frame index register scavenging to not have to check
for available registers directly and instead just let scavengeRegister()
handle it.

llvm-svn: 107880
 2010-07-08 16:49:26 +00:00
Jakob Stoklund Olesen
30aacf68b9 Convert EXTRACT_SUBREG to COPY when emitting machine instrs. 
EXTRACT_SUBREG no longer appears as a machine instruction. Use COPY instead.

Add isCopy() checks in many places using isMoveInstr() and isExtractSubreg().
The isMoveInstr hook will be removed later.

llvm-svn: 107879
 2010-07-08 16:40:22 +00:00
Jakob Stoklund Olesen
8983ea915c Remove references to INSERT_SUBREG after de-SSA. 
Fix X86InstrInfo::convertToThreeAddressWithLEA to generate COPY instead of
INSERT_SUBREG.

llvm-svn: 107878
 2010-07-08 16:40:15 +00:00
Benjamin Kramer
c1ae755ba7 Merge the duplicated iabs optimization in DAGCombiner and let it detected a few more idioms. 
llvm-svn: 107868
 2010-07-08 12:09:56 +00:00