RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-12-26 13:36:28 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity
6,339 Commits 4 Branches 5 Tags 634 MiB
beb320af87
Commit Graph

6339 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Chris Lattner
b7219c6700 Fix bug in environment setting 
llvm-svn: 6671
 2003-06-08 15:33:25 +00:00
Chris Lattner
66f5f27dcb Add #include for older GCC's 
llvm-svn: 6670
 2003-06-08 06:43:57 +00:00
Chris Lattner
326e1fb77d Fix bug: LevelRaise/2003-06-07-EmptyArrayTest.ll 
llvm-svn: 6669
 2003-06-07 21:45:42 +00:00
Chris Lattner
5bc76cec9a New testcase 
llvm-svn: 6668
 2003-06-07 21:43:56 +00:00
Chris Lattner
26c238c746 Fix compilation problem on GCC 2.9x 
llvm-svn: 6667
 2003-06-07 20:29:58 +00:00
Misha Brukman
ba5c703619 Do not hastily change the Opcode from 'r' to 'i' type if we're not actually 
SETTING the operand to be an immediate or have verified that one of the operands
is really a SignExtended or Unextended immediate value already, which warrants
an 'i' opcode.

llvm-svn: 6662
 2003-06-07 02:34:43 +00:00
Chris Lattner
51bbe7b282 Old versions of GCC doesn't have <ostream> :( 
llvm-svn: 6661
 2003-06-06 23:06:20 +00:00
Chris Lattner
68ee069591 Fix compilation problem with some versions of G++ 
llvm-svn: 6660
 2003-06-06 22:13:01 +00:00
Chris Lattner
5e34712b08 Fix problem with perror 
llvm-svn: 6659
 2003-06-06 21:09:29 +00:00
Chris Lattner
d4e4130f0a Fix warnings on Sparc 
llvm-svn: 6658
 2003-06-06 18:25:33 +00:00
Misha Brukman
4f614afd11 Print address out as hex. 
llvm-svn: 6657
 2003-06-06 09:53:28 +00:00
Misha Brukman
2f76ce01b0 Added 'r' and 'i' versions to WRCCR. 
llvm-svn: 6656
 2003-06-06 09:52:58 +00:00
Misha Brukman
d61d0211ba * Changed Bcc instructions to behave like BPcc instructions 
* BPA and BPN do not take a %cc register as a parameter
* SLL/SRL/SRA{r,i}5 are there for a reason - they are ONLY 32-bit instructions
* Likewise, SLL/SRL/SRAX{r,i}6 are only 64-bit
* Added WRCCR{r,i} opcodes

llvm-svn: 6655
 2003-06-06 09:52:23 +00:00
Misha Brukman
0bcec39bf7 Return 'int 0' instead of 'void' so that the test can be seen as successful. 
llvm-svn: 6654
 2003-06-06 08:00:40 +00:00
Misha Brukman
24db0aaa4c Return 'int 0' instead of void so that the test can be considered to pass. 
llvm-svn: 6653
 2003-06-06 07:58:29 +00:00
Misha Brukman
a8f6be985d * Removed PreSelection pass because that is now done in the JIT 
* Removed instruction scheduling as it is too slow to run in a JIT environment
* Removed other passes because they aren't necessary and can slow JIT down

llvm-svn: 6652
 2003-06-06 07:11:16 +00:00
Chris Lattner
e9a9d85aee Don't output explicit initializers for globals that are zero initialized 
llvm-svn: 6651
 2003-06-06 07:10:24 +00:00
Misha Brukman
1a3c1a6208 ::: HACK ALERT ::: HACK ALERT ::: HACK ALERT ::: HACK ALERT ::: HACK ALERT ::: 
The JIT is designed to code-generate a function at-a-time. That means that any
pass can only make local changes to its function. Period.

Because the Sparc PreSelection pass claims to be a BasicBlock pass while adding
globals to the Module, it cannot be run with the other passes, because by this
time, the globals have been output already by the JIT, and the addresses of any
globals appearing AFTER this point are not recognized.

However, the PreSelection pass is a requirement for correctness in the Sparc
codegen path, so it MUST be run.

::: HACK ALERT ::: HACK ALERT ::: HACK ALERT ::: HACK ALERT ::: HACK ALERT :::

llvm-svn: 6650
 2003-06-06 06:59:55 +00:00
Misha Brukman
6762302093 Output function address as hex. 
llvm-svn: 6649
 2003-06-06 06:52:35 +00:00
Misha Brukman
946b3a1902 Simplify test case: remove declaration of __main() and call to it. 
llvm-svn: 6648
 2003-06-06 06:50:43 +00:00
Misha Brukman
960a2c69b5 Fixed a bunch of test cases in test/Regression/Jello which could not get the 
address of a floating-point (allocated via ConstantPool) correctly.

llvm-svn: 6647
 2003-06-06 04:41:22 +00:00
Chris Lattner
437985e52c Add statistic for # machine instrs emitted 
Add GROSS HACK to get CompilationCallback to work when compiled in release mode

llvm-svn: 6646
 2003-06-06 04:00:05 +00:00
Misha Brukman
4720f1af42 * If a global is not a function, just ask the MachineCodeEmitter for the addr 
* Do not block a print statement with a DEBUG() guard if we're going to abort()

llvm-svn: 6645
 2003-06-06 03:35:37 +00:00
Misha Brukman
9e8fd867b4 The SUB*i instructions belong to a different class than their SUB*r brethren. 
llvm-svn: 6644
 2003-06-06 03:34:47 +00:00
Misha Brukman
545d95e475 All debug print statements are now output with the DEBUG() guard to make 
output clean so that tests can automatically diff the output.

llvm-svn: 6643
 2003-06-06 00:27:02 +00:00
Misha Brukman
9136d8dd0d Put all debug print statements under the DEBUG() guard to make output clean so 
that tests can automatically diff the output.

llvm-svn: 6642
 2003-06-06 00:26:11 +00:00
Misha Brukman
999c7802ab Removed debug print statement. 
llvm-svn: 6641
 2003-06-06 00:00:54 +00:00
Misha Brukman
c3b2d93a5c Fixed confusion between register classes and register types. 
Now %fcc registers are recognized correctly.

llvm-svn: 6640
 2003-06-05 23:51:10 +00:00
Misha Brukman
f0c930a86c Added missing directive to store the instruction name. 
llvm-svn: 6639
 2003-06-05 23:35:11 +00:00
Misha Brukman
6026ff3361 Moved predict and annul fields to the end of each individual instruction 
class, because they are currently unused.

llvm-svn: 6638
 2003-06-05 23:33:15 +00:00
Misha Brukman
0c06cc4fb9 Do not preset the cc register, the instructions actually use it. 
llvm-svn: 6637
 2003-06-05 23:30:27 +00:00
Misha Brukman
de307f15d4 * Stop ignoring cc registers, since we actually use them in branches. 
* Added comment as to why we are still ignoring predict and annul bits.

llvm-svn: 6636
 2003-06-05 23:15:25 +00:00
Vikram S. Adve
9dea456cbd Minor tuning -- avoid a non-inlinable function call on every operand. 
Also, reorder a couple of functions for inlining.

llvm-svn: 6635
 2003-06-05 21:12:56 +00:00
Chris Lattner
6366fa53e5 Fix (bogus) possibly uninitialized warning 
llvm-svn: 6634
 2003-06-05 21:01:26 +00:00
Misha Brukman
26e89721e8 Added lazy function resolution to the JIT. 
llvm-svn: 6633
 2003-06-05 20:52:06 +00:00
Misha Brukman
33a2ade60f * The textual output of (non-)predicted FP branches is the same. 
* Stop mapping FBcc instructions to deprecated opcodes, map to FBPcc instead.
* Fixed opf in FCMPxy instructions.

llvm-svn: 6632
 2003-06-05 20:51:37 +00:00
Chris Lattner
dec82c2ca1 Remove duplicate pass 
llvm-svn: 6631
 2003-06-05 20:51:10 +00:00
Chris Lattner
1bbfcd901c Fix bug: InstCombine/2003-06-05-BranchInvertInfLoop.ll 
llvm-svn: 6630
 2003-06-05 20:12:51 +00:00
Chris Lattner
1021b8ce62 New testcase 
llvm-svn: 6629
 2003-06-05 20:12:32 +00:00
Chris Lattner
09511fe404 Test seteq AND setne 
llvm-svn: 6628
 2003-06-05 20:11:19 +00:00
Chris Lattner
6a3d2fc70e Implement generation of cmp R, C to not use an extra register 
llvm-svn: 6627
 2003-06-05 19:30:30 +00:00
Chris Lattner
ee044c3179 Special case simple binary operator X op C 
This avoid generating a register to hold C, which in turn speeds up the
  register allocator by a lot: ~9% on 164.gzip and ~17% on 256.bzip2.  This
  also speeds up other passes.  This also speeds up execution of the program
  marginally, and makes the asm much easier to read. :)

llvm-svn: 6626
 2003-06-05 18:28:55 +00:00
Chris Lattner
c1bc144c7d Add instructions for (add|sub|and|or|xor)ri(8|16|32) 
llvm-svn: 6625
 2003-06-05 18:25:08 +00:00
Chris Lattner
060e5e326b Fix bug: Jello/2003-06-04-bzip2-bug.ll 
llvm-svn: 6624
 2003-06-05 17:15:04 +00:00
Chris Lattner
dc8209bab4 New testcase, the JIT currently handles this right, I just don't want to 
reintroduce a bug that didn't have a testcase.

llvm-svn: 6623
 2003-06-05 16:57:55 +00:00
Anand Shukla
80e3f54082 Fixed a bug so initialization code is always inserted in main 
llvm-svn: 6622
 2003-06-05 06:02:46 +00:00
Chris Lattner
eed7a2777c New testcase for PHI handling 
llvm-svn: 6621
 2003-06-05 05:38:30 +00:00
Chris Lattner
b7423ab729 Use a constant expr GEP instead of an actual instruction 
llvm-svn: 6620
 2003-06-05 04:48:18 +00:00
Misha Brukman
e8b6c4d380 All store instructions really want 'rd' in the first field. 
Special cases: STFSRx and STXFSRx - they operate on predefined rd=0 or rd=1, and
expect %fsr as the parameter in assembly. They are disabled (since not used)
until an encoding, both for code generation and output, is chosen.

llvm-svn: 6619
 2003-06-05 01:06:10 +00:00
Misha Brukman
93b1009318 Added missing 'rs1' field to F3_rdrs1imm13, 'rd' to F3_rdrs1rs2. 
llvm-svn: 6618
 2003-06-05 00:39:45 +00:00