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2336 Commits

Author SHA1 Message Date
Chris Lattner
6a8b488d78 add a note. 
llvm-svn: 99815
 2010-03-29 17:02:02 +00:00
Johnny Chen
03c2e8a36c Add NVTBLFrm to represent A8.6.406 VTBL, VTBX Vector Table Lookup Instructions. 
These instructions use byte index in a control vector (M:Vm) to lookup byte
values in a table and generate a new vector (D:Vd).  The table is specified via
a list of vectors, which can be:

{Dn}
{Dn D<n+1>}
{Dn D<n+1> D<n+2>}
{Dn D<n+1> D<n+2> D<n+3>}

llvm-svn: 99789
 2010-03-29 01:14:22 +00:00
Chris Lattner
7f2800ea6c fix integer negates to use the proper type for the zero vectors, 
this also depends on the new "bitconvert dropping" behavior just
added to tblgen.

llvm-svn: 99757
 2010-03-28 08:39:10 +00:00
Chris Lattner
36a0df5c96 fix vnot matching to explicitly specify the type of the 
input to be v8i8 or v16i8, which buildvectors get canonicalized to.

This allows the patterns that were previously using a bare 'vnot' to
match, before they couldn't.

llvm-svn: 99754
 2010-03-28 08:08:07 +00:00
Bob Wilson
6d9296abc6 Fix indentation. 
llvm-svn: 99705
 2010-03-27 04:01:23 +00:00
Bob Wilson
be89c51aa3 Add a format argument to the N3V and N3VX classes, removing the N3Vf class. 
llvm-svn: 99704
 2010-03-27 03:56:52 +00:00
Johnny Chen
794a9a3941 Add NVMulSLFrm to represent "3-register multiply with scalar" operations and set 
it as the format for the appropriate N3V*SL*<> classes.  These instructions
require special handling of the M:Vm field which encodes the restricted Dm and
the lane index within Dm.

Examples are A8.6.325 VMLA, VMLAL, VMLS, VMLSL (by scalar):

	vmlal.s32	q3, d2, d10[0]

llvm-svn: 99690
 2010-03-27 01:03:13 +00:00
Jim Grosbach
f884dba43d Thumb2 storeFrom/LoadToStackSlot() need to handle tGPR regs directly, not pass 
through to the generic version. The generic functions use STR/LDR, but T2
needs the t2STR/t2LDR instead so we get the addressing mode correct.

llvm-svn: 99678
 2010-03-27 00:09:12 +00:00
Johnny Chen
0763231e02 Remove the duplicate multiclass N3VSh_QHSD and use N3VInt_QHSD which is modified 
to now take a format argument.  N3VDInt<> and N3VQInt<> are modified to take a
format argument as well.

llvm-svn: 99676
 2010-03-26 23:49:07 +00:00
Johnny Chen
ca1d7dcfe4 Add NVExtFrm to represent NEON Vector Extract Instructions, that uses Inst{11-8} 
to encode the byte location of the extracted result in the concatenation of the
operands, from the least significant end.

Modify VEXTd and VEXTq classes to use the format.

llvm-svn: 99659
 2010-03-26 22:28:56 +00:00
Johnny Chen
4a97a176e7 Add N3RegVShFrm to represent 3-Register Vector Shift Instructions, which do not 
follow the N3RegFrm's operand order of D:Vd N:Vn M:Vm.  The operand order of
N3RegVShFrm is D:Vd M:Vm N:Vn (notice that M:Vm is the first src operand).

Add a parent class N3Vf which requires passing a Format argument and which the
N3V class is modified to inherit from.  N3V class represents the "normal"
3-Register NEON Instructions with N3RegFrm.

Also add a multiclass N3VSh_QHSD to represent clusters of NEON 3-Register Shift
Instructions and replace 8 invocations with it.

llvm-svn: 99655
 2010-03-26 21:26:28 +00:00
Jim Grosbach
97d626c850 vldm/vstm can only do up to 16 double-word registers at a time. 
Radar 7797856

llvm-svn: 99630
 2010-03-26 18:41:09 +00:00
Johnny Chen
c986f10733 Add N3RegFrm to represent "NEON 3 vector register format" instructions. 
Examples are VABA (Vector Absolute Difference and Accumulate), VABAL (Vector
Absolute Difference and Accumulate Long), and VABD (Vector Absolute Difference).

llvm-svn: 99628
 2010-03-26 18:32:20 +00:00
Johnny Chen
a8b02d6451 Add N2RegVShLFrm and N2RegVShRFrm formats so that the disassembler can easily 
dispatch to the appropriate routines to handle the different interpretations of
the shift amount encoded in the imm6 field.  The Vd, Vm fields are interpreted
the same between the two, though.

See, for example, A8.6.367 VQSHL, VQSHLU (immediate) for N2RegVShLFrm format and
A8.6.368 VQSHRN, VQSHRUN for N2RegVShRFrm format.

llvm-svn: 99590
 2010-03-26 01:07:59 +00:00
Jim Grosbach
2a0b14a387 switch the flag for using NEON for SP floating point to a subtarget 'feature'. 
Re-commit. This time complete with testsuite updates.

llvm-svn: 99570
 2010-03-25 23:47:34 +00:00
Jim Grosbach
97d5bc2b86 need to fix 'make check' tests first. revert for a moment. 
llvm-svn: 99569
 2010-03-25 23:34:05 +00:00
Jim Grosbach
7e87ba79e6 switch the flag for using NEON for SP floating point to a subtarget 'feature' 
llvm-svn: 99568
 2010-03-25 23:32:19 +00:00
Johnny Chen
d56897bddc Removed instruction class NI from ARMInstrFormats.td. 
It doesn't seem to be used anywhere.

llvm-svn: 99566
 2010-03-25 23:11:56 +00:00
Jim Grosbach
b97ff2a4c1 switch the use-vml[as] instructions flag to a subtarget 'feature' 
llvm-svn: 99565
 2010-03-25 23:11:16 +00:00
Johnny Chen
38c9f64289 Add NVDupLnFrm and change NVDupLane class to use that format. 
llvm-svn: 99557
 2010-03-25 21:49:12 +00:00
Jim Grosbach
0975d55c8e ARM cortex-a8 doesn't do vmla/vmls well. disable them by default for that cpu 
llvm-svn: 99549
 2010-03-25 20:48:50 +00:00
Johnny Chen
58278a364d Add NVCVTFrm (NEON Convert with fractional bits immediate) and modify N2VImm to 
expect a Format arg.  N2VCvtD/N2VCvtQ are modified to use the NVCVTFrm format.

llvm-svn: 99548
 2010-03-25 20:39:04 +00:00
Johnny Chen
cc491eff10 Added a new instruction class NVDupLane to be inherited by VDUPLND and VDUPLNQ, 
instead of the current N2V.  Format of NVDupLane instances are set to NEONFrm
currently.

llvm-svn: 99518
 2010-03-25 17:01:27 +00:00
Jim Grosbach
d285f71b9a Make the use of the vmla and vmls VFP instructions controllable via cmd line. 
Preliminary testing shows significant performance wins by not using these
instructions.

llvm-svn: 99436
 2010-03-24 22:31:46 +00:00
Johnny Chen
f53b3e5b12 Trivial formating change. 
llvm-svn: 99428
 2010-03-24 21:25:07 +00:00
Johnny Chen
3e5750fc46 Reverted r99326 which added NVdVmVCVTFrm, and later renamed to NVCVTFrm. 
NVCVTFrm will later be used to describe "vcvt with fractional bits".

llvm-svn: 99415
 2010-03-24 19:47:14 +00:00
Johnny Chen
31c01c1811 Reverted r99376. The disassembler will deal with the 2-reg format of these two 
N3VX instructions using special case code.

llvm-svn: 99409
 2010-03-24 18:46:34 +00:00
Jim Grosbach
7dc50db8fa tweak the arm if conversion heuristic 
llvm-svn: 99402
 2010-03-24 16:15:14 +00:00
Johnny Chen
d31726dba1 Mark VMOVDneon and VMOVQ as having the N2RegFrm form to help the disassembler. 
llvm-svn: 99376
 2010-03-24 01:29:25 +00:00
Johnny Chen
dabf739480 Renamed NVdVmImmFrm and NVdVmVCVTFrm to the more proper N2RegFrm and NVCVTFrm, 
respectively, and add some more comment.

llvm-svn: 99373
 2010-03-24 00:57:50 +00:00
Jim Grosbach
b19d22fcae try being more permissive for if-conversion on ARM V7. see what the nightly 
test run permformance numbers say as to whether it helps.

llvm-svn: 99355
 2010-03-24 00:03:13 +00:00
Johnny Chen
b7f2a26117 Renamed NVdImmFrm to N1RegModImmFrm. 
llvm-svn: 99344
 2010-03-23 23:09:14 +00:00
Johnny Chen
d97eb200cf Fix typo in the comment for N3VX class. 
llvm-svn: 99328
 2010-03-23 21:35:03 +00:00
Johnny Chen
8249bce25e Add comment. 
llvm-svn: 99327
 2010-03-23 21:30:12 +00:00
Johnny Chen
415ce90919 Add New NEON Format NVdVmVCVTFrm. 
Converted some of the NEON vcvt instructions to this format.

llvm-svn: 99326
 2010-03-23 21:25:38 +00:00
Johnny Chen
81fb570fda Add New NEON Format NVdVmImmFrm. 
llvm-svn: 99322
 2010-03-23 20:40:44 +00:00
Bob Wilson
195c570fd3 Fix VLDMQ and VSTMQ instructions to use the correct encoding and address modes. 
These instructions are only needed for codegen, so I've removed all the
explicit encoding bits for now; they should be set in the same way as the for
VLDMD and VSTMD whenever we add encodings for VFP.  The use of addrmode5
requires that the instructions be custom-selected so that the number of
registers can be set in the AM5Opc value.

llvm-svn: 99309
 2010-03-23 18:54:46 +00:00
Bob Wilson
672147e9a2 Fix bad indentation, 80-column violations, and trailing whitespace. 
llvm-svn: 99295
 2010-03-23 17:23:59 +00:00
Johnny Chen
00ac54b896 Add New NEON Format NVdImmFrm. 
Ref: A7.4.6 One register and a modified immediate value.

llvm-svn: 99288
 2010-03-23 16:43:47 +00:00
Bob Wilson
8ba51dc0bd Rename some instructions to match the corresponding NEON opcode. 
llvm-svn: 99266
 2010-03-23 06:26:18 +00:00
Bob Wilson
58c4740582 Change VST1 instructions for loading Q register values to operate on pairs 
of D registers.  Add a separate VST1q instruction with a Q register
source operand for use by storeRegToStackSlot.

llvm-svn: 99265
 2010-03-23 06:20:33 +00:00
Bob Wilson
2764399dd8 Change VLD1 instructions for loading Q register values to operate on pairs 
of D registers.  Add a separate VLD1q instruction with a Q register
destination operand for use by loadRegFromStackSlot.

llvm-svn: 99261
 2010-03-23 05:25:43 +00:00
Bob Wilson
0741acde00 Rename one more NEON instruction that I missed earlier. 
llvm-svn: 99201
 2010-03-22 20:31:39 +00:00
Bob Wilson
80b4f21ab7 Regroup some instructions. No functional change. 
llvm-svn: 99192
 2010-03-22 18:22:06 +00:00
Bob Wilson
f23a45e151 Rename some VLD1/VST1 instructions to match the implementation, i.e., the 
corresponding NEON instructions, instead of operation they are currently
used for.

llvm-svn: 99189
 2010-03-22 18:13:18 +00:00
Bob Wilson
8ff1029669 Remove some redundant instruction classes. 
llvm-svn: 99187
 2010-03-22 18:02:38 +00:00
Bob Wilson
0e5d42fb54 Refactor instruction encoding arguments for VLDnLN/VSTnLN classes to 
specify encoding bits in arguments instead of "let" expressions.

llvm-svn: 99185
 2010-03-22 16:43:10 +00:00
Jeffrey Yasskin
cf13a6f8bb Don't leak a MachineInstruction from Thumb1InstrInfo::restoreCalleeSavedRegisters. 
llvm-svn: 99182
 2010-03-22 16:13:21 +00:00
Daniel Dunbar
2c99d47702 TargetRegistry: Fix create{AsmInfo,MCDisassembler} to return non-const objects. 
llvm-svn: 99097
 2010-03-20 22:36:22 +00:00
Bob Wilson
e5614d6b2d pr6652: Use LDM to restore PC to the return address on ARMv4. 
Patch by John Tytgat!

llvm-svn: 99096
 2010-03-20 22:20:40 +00:00