Commit Graph

45021 Commits

Author SHA1 Message Date
Bruno Cardoso Lopes
c0f87c11d6 Change instruction names for consistency
llvm-svn: 123930
2011-01-20 18:36:07 +00:00
Bruno Cardoso Lopes
5f06c0aa3b Add cdp/cdp2 instructions for thumb/thumb2
llvm-svn: 123929
2011-01-20 18:32:09 +00:00
Bruno Cardoso Lopes
3584c02d83 - Use a more appropriate name for Owen's ARM Parser isMCR hack since the same operands can be present
in cdp/cdp2 instructions. Also increase the hack with cdp/cdp2 instructions.
- Fix the encoding of cdp/cdp2 instructions for ARM (no thumb and thumb2 yet) and add testcases for t
hem.

llvm-svn: 123927
2011-01-20 18:06:58 +00:00
Jakob Stoklund Olesen
60743dd45f SplitKit requires that all defs are in place before calling useIntv().
The value mapping gets confused about which original values have multiple new
definitions so they may need phi insertions.

This could probably be simplified by letting enterIntvBefore() take a live range
to be added following the instruction. As long as the range stays inside the
same basic block, value mapping shouldn't be a problem.

llvm-svn: 123926
2011-01-20 17:45:23 +00:00
Jakob Stoklund Olesen
360b0921ac Add LiveIntervalMap::dumpCache() to print out the cache used by the ssa update algorithm.
llvm-svn: 123925
2011-01-20 17:45:20 +00:00
Bruno Cardoso Lopes
75712e8a7a Add mcr*2 and mr*c2 support to thumb2 targets
llvm-svn: 123919
2011-01-20 16:58:48 +00:00
Bruno Cardoso Lopes
f377d1721e Add mcr* and mr*c support to thumb targets
llvm-svn: 123917
2011-01-20 16:35:57 +00:00
Kalle Raiskila
070fb5e54d Allow sign-extending of i8 and i16 to i128 on SPU.
llvm-svn: 123912
2011-01-20 15:49:06 +00:00
Duncan Sands
1faa8712c9 At -O123 the early-cse pass is run before instcombine has run. According to my
auto-simplier the transform most missed by early-cse is (zext X) != 0 -> X != 0.
This patch adds this transform and some related logic to InstructionSimplify
and removes some of the logic from instcombine (unfortunately not all because
there are several situations in which instcombine can improve things by making
new instructions, whereas instsimplify is not allowed to do this).  At -O2 this
often results in more than 15% more simplifications by early-cse, and results in
hundreds of lines of bitcode being eliminated from the testsuite.  I did see some
small negative effects in the testsuite, for example a few additional instructions
in three programs.  One program, 483.xalancbmk, got an additional 35 instructions,
which seems to be due to a function getting an additional instruction and then
being inlined all over the place.

llvm-svn: 123911
2011-01-20 13:21:55 +00:00
Bruno Cardoso Lopes
0312bb222e Refactor mcr* and mr*c instructions into classes with the same encoding. No functionality change.
llvm-svn: 123910
2011-01-20 13:17:59 +00:00
Eric Christopher
d17b5b7988 My editor's indent went crazy. Fix.
llvm-svn: 123909
2011-01-20 08:56:34 +00:00
Eric Christopher
f7579ff174 Expand invalid return values for umulo and smulo. Handle these similarly
to add/sub by doing the normal operation and then checking for overflow
afterwards. This generally relies on the DAG handling the later invalid
operations as well.

Fixes the 64-bit part of rdar://8622122 and rdar://8774702.

llvm-svn: 123908
2011-01-20 08:54:28 +00:00
Evan Cheng
d9fdc9771e Correct itinerary entry for t2MOV_pic_ga_add_pc.
llvm-svn: 123907
2011-01-20 08:43:03 +00:00
Evan Cheng
6dc21c7358 Sorry, several patches in one.
TargetInstrInfo:
Change produceSameValue() to take MachineRegisterInfo as an optional argument.
When in SSA form, targets can use it to make more aggressive equality analysis.

Machine LICM:
1. Eliminate isLoadFromConstantMemory, use MI.isInvariantLoad instead.
2. Fix a bug which prevent CSE of instructions which are not re-materializable.
3. Use improved form of produceSameValue.

ARM:
1. Teach ARM produceSameValue to look pass some PIC labels.
2. Look for operands from different loads of different constant pool entries
   which have same values.
3. Re-implement PIC GA materialization using movw + movt. Combine the pair with
   a "add pc" or "ldr [pc]" to form pseudo instructions. This makes it possible
   to re-materialize the instruction, allow machine LICM to hoist the set of
   instructions out of the loop and make it possible to CSE them. It's a bit
   hacky, but it significantly improve code quality.
4. Some minor bug fixes as well.

With the fixes, using movw + movt to materialize GAs significantly outperform the
load from constantpool method. 186.crafty and 255.vortex improved > 20%, 254.gap
and 176.gcc ~10%.

llvm-svn: 123905
2011-01-20 08:34:58 +00:00
Michael J. Spencer
d54bad63f7 Object: Add ELF support.
llvm-svn: 123896
2011-01-20 06:38:47 +00:00
Michael J. Spencer
d4d4ab7712 Object: Add COFF Support.
llvm-svn: 123895
2011-01-20 06:38:34 +00:00
Andrew Trick
bf079d8831 Selection DAG scheduler register pressure heuristic fixes.
Added a check for already live regs before claiming HighRegPressure.
Fixed a few cases of checking the wrong number of successors.
Added some tracing until these heuristics are better understood.

llvm-svn: 123892
2011-01-20 06:21:59 +00:00
Jakob Stoklund Olesen
ea33059ff5 Check that a live range exists before shortening it. This fixes PR8989.
The live range may have been deleted earlier because of rematerialization.

llvm-svn: 123891
2011-01-20 06:20:02 +00:00
Jakob Stoklund Olesen
bb94da29b2 Add hidden -verify-coalescing to run the machine code verifier before and after
register coalescing.

llvm-svn: 123890
2011-01-20 06:20:00 +00:00
Venkatraman Govindaraju
5280b2876f Sparc backend: Implements a delay slot filler that attempt to fill delay slots
with useful instructions.

llvm-svn: 123884
2011-01-20 05:08:26 +00:00
Cameron Zwarich
bf70725ae3 Update a comment.
llvm-svn: 123879
2011-01-20 03:58:43 +00:00
Jakob Stoklund Olesen
c387993232 Fix bug found by new clang warning.
llvm-svn: 123872
2011-01-20 02:43:19 +00:00
Eric Christopher
58f8058502 Use only one API at a time.
llvm-svn: 123866
2011-01-20 01:29:23 +00:00
Eric Christopher
1b0e5debb4 If we can, lower the multiply part of a umulo/smulo call to a libcall
with an invalid type then split the result and perform the overflow check
normally.

Fixes the 32-bit parts of rdar://8622122 and rdar://8774702.

llvm-svn: 123864
2011-01-20 00:29:24 +00:00
Devang Patel
729c5e59af Fix debug info for merged global.
llvm-svn: 123862
2011-01-20 00:02:16 +00:00
Jakob Stoklund Olesen
69294ae8d7 Divert Hopfield network debug output. It is very noisy.
llvm-svn: 123859
2011-01-19 23:14:59 +00:00
Jakob Stoklund Olesen
c47bd85657 Don't accidentally leave small gaps in the live ranges when leaving the active
interval after an instruction. The leaveIntvAfter() method only adds liveness
from the instruction's boundary index to the inserted copy.

Ideally, SplitKit should be smarter about this, perhaps by combining useIntv()
and leaveIntvAfter() into one method that guarantees continuity.

llvm-svn: 123858
2011-01-19 23:14:56 +00:00
Jim Grosbach
868d2877dc Make sure to propogate the error code when we fail to parse a modifier.
llvm-svn: 123857
2011-01-19 23:06:07 +00:00
Devang Patel
574e10fa1e Fix register address expression. Patch by Ken Dyck.
llvm-svn: 123856
2011-01-19 23:04:47 +00:00
Jakob Stoklund Olesen
77738dd84e Implement RAGreedy::splitAroundRegion and remove loop splitting.
Region splitting includes loop splitting as a subset, and it is more generic.
The splitting heuristics for variables that are live in more than one block are
now:

1. Try to create a region that covers multiple basic blocks.
2. Try to create a new live range for each block with multiple uses.
3. Spill.

Steps 2 and 3 are similar to what the standard spiller is doing.

llvm-svn: 123853
2011-01-19 22:11:48 +00:00
Nick Lewycky
51c13384f5 Similarly, analyze truncate through multiply.
llvm-svn: 123842
2011-01-19 18:56:00 +00:00
Nick Lewycky
9867e58096 Add a missed SCEV fold that is required to continue analyzing the IR produced
by indvars through the scev expander.

trunc(add x, y) --> add(trunc x, y). Currently SCEV largely folds the other way
which is probably wrong, but preserved to minimize churn. Instcombine doesn't
do this fold either, demonstrating a missed optz'n opportunity on code doing
add+trunc+add.

llvm-svn: 123838
2011-01-19 16:59:46 +00:00
Bruno Cardoso Lopes
0f7a30b1cb Fix the encoding of mrrc and mcrr family of instructions. Also add testcases for mcr and mrc
llvm-svn: 123837
2011-01-19 16:56:52 +00:00
Rafael Espindola
ce499efe1d Add unnamed_addr when we can show that address of a global is not used.
llvm-svn: 123834
2011-01-19 16:32:21 +00:00
Nick Lewycky
5a538b62ca Add a missing SCEV simplification sext(zext x) --> zext x.
llvm-svn: 123832
2011-01-19 15:56:12 +00:00
Daniel Dunbar
dd1dd698f0 ARM/ISel: Factor out isScaledConstantInRange() helper.
llvm-svn: 123823
2011-01-19 15:12:16 +00:00
Andrew Trick
305613b87a For ARM subtargets with useNEONForSinglePrecisionFP, double count uses
of the floating point types less than 64-bits. It's somewhat of a temporary
hack but forces more accurate modeling of register pressure and results
in fewer spills.

llvm-svn: 123811
2011-01-19 02:35:27 +00:00
Andrew Trick
cf6999ed86 whitespace
llvm-svn: 123810
2011-01-19 02:26:13 +00:00
Evan Cheng
7e2b414953 Don't forget to emit the load from indirect symbol when using movw + movt to materialize GA indirect symbols.
llvm-svn: 123809
2011-01-19 02:16:49 +00:00
Bruno Cardoso Lopes
e0f8fee637 Create two new generic classes to represent the following VMRS/VMSR variations:
vmrs  reg, fpexc
vmrs  reg, fpsid
vmsr  fpexc, reg
vmsr  fpsid, reg

llvm-svn: 123783
2011-01-18 21:58:20 +00:00
Bruno Cardoso Lopes
82c6fe3dfe Fix MRS encoding for arm and thumb.
llvm-svn: 123778
2011-01-18 21:31:35 +00:00
Bruno Cardoso Lopes
6e4c5af01e Fix the encoding of t2ISB by using the right class and also parse it correctly
llvm-svn: 123776
2011-01-18 21:17:09 +00:00
Dan Gohman
df668227fb Teach BasicAA to return PartialAlias in cases where both pointers
are pointing to the same object, one pointer is accessing the entire
object, and the other is access has a non-zero size. This prevents
TBAA from kicking in and saying NoAlias in such cases.

llvm-svn: 123775
2011-01-18 21:16:06 +00:00
Jakob Stoklund Olesen
c0ff5356d4 Add RAGreedy methods for splitting live ranges around regions.
Analyze the live range's behavior entering and leaving basic blocks. Compute an
interference pattern for each allocation candidate, and use SpillPlacement to
find an optimal region where that register can be live.

This code is still not enabled.

llvm-svn: 123774
2011-01-18 21:13:27 +00:00
Bruno Cardoso Lopes
c1e21b06b9 Follow the current hack set and enable the correct parsing of bkpt while in thumb mode.
llvm-svn: 123772
2011-01-18 20:55:11 +00:00
Chris Lattner
4832a9d32c fix rdar://8878965, a regression I introduced with the recent
llvm.objectsize changes.

llvm-svn: 123771
2011-01-18 20:53:04 +00:00
Bruno Cardoso Lopes
94247155c4 Add support for parsing and encoding ARM's official syntax for the BFI instruction
llvm-svn: 123770
2011-01-18 20:45:56 +00:00
Jim Grosbach
6de3a4f76f Add a FIXME.
llvm-svn: 123769
2011-01-18 19:59:19 +00:00
Bruno Cardoso Lopes
13cefe452d Ensure Mips::GP is properly reloaded after a function call. Patch by Sasa Stankovic
llvm-svn: 123768
2011-01-18 19:50:18 +00:00
Bruno Cardoso Lopes
2d509b8b40 Negative zero is not legal on mips. Patch by Sasa Stankovic
llvm-svn: 123766
2011-01-18 19:41:41 +00:00