RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2026-07-22 11:46:24 -04:00
Code Issues 2 Packages Projects Releases 7 Wiki Activity
194,531 Commits 6 Branches 8 Tags
cfeebf984895d0dc436daf6ccdcbbfceed7f94fa
Commit Graph

4 Commits

Author SHA1 Message Date
Reid Kleckner 9f8d106c94 Prune a LegacyDivergenceAnalysis and MachineLoopInfo include each 
Now X86ISelLowering doesn't depend on many IR analyses.

llvm-svn: 375320
 2019-10-19 01:31:09 +00:00
Matt Arsenault ae5999e106 GlobalISel: Remove unsigned variant of SrcOp 
Force using Register.

One downside is the generated register enums require explicit
conversion.

llvm-svn: 364194
 2019-06-24 16:16:12 +00:00
Matt Arsenault 0738f328d7 CodeGen: Introduce a class for registers 
Avoids using a plain unsigned for registers throughoug codegen.
Doesn't attempt to change every register use, just something a little
more than the set needed to build after changing the return type of
MachineOperand::getReg().

llvm-svn: 364191
 2019-06-24 15:50:29 +00:00
Tim Northover fefb8f4f37 CodeGen: factor out swifterror value tracking. 
llvm-svn: 361607
 2019-05-24 08:39:43 +00:00