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52 Commits

Author SHA1 Message Date
Jim Grosbach
1128a47289 cortex m4 has floating point support, but only single precision. 
llvm-svn: 110810
 2010-08-11 15:44:15 +00:00
Evan Cheng
f8604b772e Report error if codegen tries to instantiate a ARM target when the cpu does support it. e.g. cortex-m* processors. 
llvm-svn: 110798
 2010-08-11 07:17:46 +00:00
Evan Cheng
273160895e Add ARM Archv6M and let it implies FeatureDB (having dmb, etc.) 
llvm-svn: 110795
 2010-08-11 06:51:54 +00:00
Evan Cheng
5fca4ca5f9 - Add subtarget feature -mattr=+db which determine whether an ARM cpu has the 
memory and synchronization barrier dmb and dsb instructions.
- Change instruction names to something more sensible (matching name of actual
  instructions).
- Added tests for memory barrier codegen.

llvm-svn: 110785
 2010-08-11 06:22:01 +00:00
Evan Cheng
15d23d4966 Change -prefer-32bit-thumb to attribute -mattr=+32bit instead to disable more 32-bit to 16-bit optimizations. 
llvm-svn: 110584
 2010-08-09 18:35:19 +00:00
Evan Cheng
67743f2057 Add an ARM "feature". Cortex-a8 fp comparison is very slow (> 20 cycles). 
llvm-svn: 108256
 2010-07-13 19:21:50 +00:00
Shantonu Sen
0fc6812809 Fix "warning: extra ';' inside a struct or union" when building llvm with clang 
llvm-svn: 103179
 2010-05-06 14:57:47 +00:00
Jim Grosbach
e04cc6cb43 Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/pack 
instructions to subtarget features and update tests to reflect.
PR5717.

llvm-svn: 103136
 2010-05-05 23:44:43 +00:00
Jim Grosbach
3630aff780 Add initial support for ARMv7M subtarget and cortex-m3 cpu. Patch by 
Jordy <snhjordy@gmail.com>.

Followup patches will add some tests and adjust to use Subtarget features
for the instructions.

llvm-svn: 103119
 2010-05-05 20:44:35 +00:00
Dan Gohman
0e0b8cf9fd Add const qualifiers to CodeGen's use of LLVM IR constructs. 
llvm-svn: 101334
 2010-04-15 01:51:59 +00:00
Jim Grosbach
b97ff2a4c1 switch the use-vml[as] instructions flag to a subtarget 'feature' 
llvm-svn: 99565
 2010-03-25 23:11:16 +00:00
Jim Grosbach
d285f71b9a Make the use of the vmla and vmls VFP instructions controllable via cmd line. 
Preliminary testing shows significant performance wins by not using these
instructions.

llvm-svn: 99436
 2010-03-24 22:31:46 +00:00
Anton Korobeynikov
90fcfccc91 Add substarget feature for FP16 
llvm-svn: 98503
 2010-03-14 18:42:38 +00:00
Bob Wilson
b7efefe008 Lower small memcpys to load/stores on Thumb2. 
Radar 7686922.

llvm-svn: 98210
 2010-03-11 00:20:49 +00:00
Anton Korobeynikov
e0e616a74d Initial bits of ARMv4-only support. 
Patch by John Tytgat!

llvm-svn: 97886
 2010-03-06 19:39:36 +00:00
Bob Wilson
b293fe32cb Remove isProfitableToDuplicateIndirectBranch target hook. It is profitable 
for all the processors where I have tried it, and even when it might not help
performance, the cost is quite low.  The opportunities for duplicating
indirect branches are limited by other factors so code size does not change
much due to tail duplicating indirect branches aggressively.

llvm-svn: 90144
 2009-11-30 18:35:03 +00:00
Anton Korobeynikov
0f885eb7fd Materialize global addresses via movt/movw pair, this is always better 
than doing the same via constpool:
1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2.
2. Load from constpool might stall up to 300 cycles due to cache miss.
3. Movt/movw does not use load/store unit.
4. Less constpool entries => better compiler performance.

This is only enabled on ELF systems, since darwin does not have needed
relocations (yet).

llvm-svn: 89720
 2009-11-24 00:44:37 +00:00
Bob Wilson
6b68bd153a Add a target hook to allow changing the tail duplication limit based on the 
contents of the block to be duplicated.  Use this for ARM Cortex A8/9 to
be more aggressive tail duplicating indirect branches, since it makes it
much more likely that they will be predicted in the branch target buffer.
Testcase coming soon.

llvm-svn: 89187
 2009-11-18 03:34:27 +00:00
David Goodwin
e1d06f2239 Allow target to specify regclass for which antideps will only be broken along the critical path. 
llvm-svn: 88682
 2009-11-13 19:52:48 +00:00
David Goodwin
93a4f29c67 Fixed to address code review. No functional changes. 
llvm-svn: 86634
 2009-11-10 00:48:55 +00:00
David Goodwin
538f9c25f8 Allow targets to specify register classes whose member registers should not be renamed to break anti-dependencies. 
llvm-svn: 86628
 2009-11-10 00:15:47 +00:00
David Goodwin
f6199e95b0 Break anti-dependence breaking out into its own class. 
llvm-svn: 85127
 2009-10-26 16:59:04 +00:00
David Goodwin
82c1dd9754 Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none. 
llvm-svn: 84911
 2009-10-22 23:19:17 +00:00
Evan Cheng
e1fbdc5244 Change createPostRAScheduler so it can be turned off at llc -O1. 
llvm-svn: 84273
 2009-10-16 21:06:15 +00:00
David Goodwin
a282690f82 Remove -post-RA-schedule flag and add a TargetSubtarget method to enable post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8. 
llvm-svn: 83122
 2009-09-30 00:10:16 +00:00
Evan Cheng
41e87f2f13 Reference to hidden symbols do not have to go through non-lazy pointer in non-pic mode. rdar://7187172. 
llvm-svn: 80904
 2009-09-03 07:04:02 +00:00
Evan Cheng
d7a07ab112 Let Darwin linker auto-synthesize stubs and lazy-pointers. This deletes a bunch of nasty code in ARM asm printer. 
llvm-svn: 80404
 2009-08-28 23:18:09 +00:00
Jim Grosbach
3c898a99bd Whitespace cleanup. Remove trailing whitespace. 
llvm-svn: 78666
 2009-08-11 15:33:49 +00:00
David Goodwin
47064aa1c6 By default, for cortex-a8 use NEON for single-precision FP. 
llvm-svn: 78200
 2009-08-05 16:01:19 +00:00
David Goodwin
99adffe5f2 Initial support for single-precision FP using NEON. Added "neonfp" attribute to enable. Added patterns for some binary FP operations. 
llvm-svn: 78081
 2009-08-04 17:53:06 +00:00
Daniel Dunbar
0b82c938fe Normalize Subtarget constructors to take a target triple string instead of 
Module*.

Also, dropped uses of TargetMachine where unnecessary. The only target which
still takes a TargetMachine& is Mips, I would appreciate it if someone would
normalize this to match other targets.

llvm-svn: 77918
 2009-08-02 22:11:08 +00:00
Evan Cheng
b70366baa4 isThumb2 really should mean thumb2 only, not thumb2+. 
llvm-svn: 74871
 2009-07-06 22:29:14 +00:00
Evan Cheng
57bb186a0c Change the meaning of predicate hasThumb2 to mean thumb2 ISA is available, not that it's in thumb mode and thumb2 is available. Added isThumb2 predicate to replace the old predicate. 
llvm-svn: 74692
 2009-07-02 06:38:40 +00:00
Bob Wilson
38779c951a Revert 74164. We'll want to use this method later. 
llvm-svn: 74176
 2009-06-25 16:03:07 +00:00
Bob Wilson
ef8fd818bf Remove unused hasV6T2Ops method. We already have a separate feature to 
identify Thumb2.

llvm-svn: 74164
 2009-06-25 05:20:31 +00:00
Evan Cheng
f671ce4eba Latency information for ARM v6. It's rough and not yet hooked up. Right now we are only using branch latency to determine if-conversion limits. 
llvm-svn: 73747
 2009-06-19 01:51:50 +00:00
Evan Cheng
7426d278ae Remove UseThumbBacktraces. Just check if subtarget is darwin. 
llvm-svn: 73734
 2009-06-18 23:14:30 +00:00
Anton Korobeynikov
2670a363da Rename methods for the sake of consistency. 
llvm-svn: 73428
 2009-06-15 21:46:20 +00:00
Anton Korobeynikov
52b2898854 Separate V6 from V6T2 since the latter has some extra nice instructions 
llvm-svn: 73085
 2009-06-08 21:20:36 +00:00
Anton Korobeynikov
7e9e1b3e1f Add helper for checking of Thumb1 mode 
llvm-svn: 73080
 2009-06-08 20:31:02 +00:00
Anton Korobeynikov
e7e9118514 Implement review feedback. Make thumb2 'normal' subtarget feature 
llvm-svn: 72698
 2009-06-01 20:00:48 +00:00
Anton Korobeynikov
4f5b1ef545 Add placeholder for thumb2 stuff 
llvm-svn: 72593
 2009-05-29 23:41:08 +00:00
Anton Korobeynikov
1fe3d6d47b Add ARMv7 architecture, Cortex processors and different FPU modes handling. 
llvm-svn: 72337
 2009-05-23 19:51:43 +00:00
Anton Korobeynikov
34fc85e2ee Propagate CPU string out of SubtargetFeatures 
llvm-svn: 72335
 2009-05-23 19:50:50 +00:00
Dan Gohman
15edbf989f Drop ISD::MEMSET, ISD::MEMMOVE, and ISD::MEMCPY, which are not Legal 
on any current target and aren't optimized in DAGCombiner. Instead
of using intermediate nodes, expand the operations, choosing between
simple loads/stores, target-specific code, and library calls,
immediately.

Previously, the code to emit optimized code for these operations
was only used at initial SelectionDAG construction time; now it is
used at all times. This fixes some cases where rep;movs was being
used for small copies where simple loads/stores would be better.

This also cleans up code that checks for alignments less than 4;
let the targets make that decision instead of doing it in
target-independent code. This allows x86 to use rep;movs in
low-alignment cases.

Also, this fixes a bug that resulted in the use of rep;stos for
memsets of 0 with non-constant memory size when the alignment was
at least 4. It's better to use the library in this case, which
can be significantly faster when the size is large.

This also preserves more SourceValue information when memory
intrinsics are lowered into simple loads/stores.

llvm-svn: 49572
 2008-04-12 04:36:06 +00:00
Chris Lattner
ad9a6ccb83 Remove attribution from file headers, per discussion on llvmdev. 
llvm-svn: 45418
 2007-12-29 20:36:04 +00:00
Rafael Espindola
27a8907a7c Make ARM and X86 LowerMEMCPY identical by moving the isThumb check into getMaxInlineSizeThreshold 
and by restructuring the X86 version.

New I just have to move this to a common place :-)

llvm-svn: 43554
 2007-10-31 14:39:58 +00:00
Rafael Espindola
fae98471a9 Make ARM an X86 memcpy expansion more similar to each other. 
Now both subtarget define getMaxInlineSizeThreshold and the expansion uses it.

This should not change generated code.

llvm-svn: 43552
 2007-10-31 11:52:06 +00:00
Evan Cheng
2d4b1cb0ca Added -march=thumb; removed -enable-thumb. 
llvm-svn: 34521
 2007-02-23 03:14:31 +00:00
Lauro Ramos Venancio
ff9f78e230 Add ABI information to ARM subtarget. 
llvm-svn: 34245
 2007-02-13 19:52:28 +00:00