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81 Commits

Author SHA1 Message Date
Bruno Cardoso Lopes
d13d8c2562 Add AVX only vzeroall and vzeroupper instructions 
llvm-svn: 109002
 2010-07-21 08:56:24 +00:00
Bruno Cardoso Lopes
a7efb29695 Add new AVX vmaskmov instructions, and also fix the VEX encoding bits to support it 
llvm-svn: 108983
 2010-07-21 02:46:58 +00:00
Bruno Cardoso Lopes
7bc71d2d0a AVX 256-bit conversion instructions 
Add the x86 VEX_L form to handle special cases where VEX_L must be set.

llvm-svn: 108274
 2010-07-13 21:07:28 +00:00
Bruno Cardoso Lopes
3676e24b67 Start the support for AVX instructions with 256-bit %ymm registers. A couple of 
notes:
- The instructions are being added with dummy placeholder patterns using some 256
  specifiers, this is not meant to work now, but since there are some multiclasses
  generic enough to accept them,  when we go for codegen, the stuff will be already
  there.
- Add VEX encoding bits to support YMM
- Add MOVUPS and MOVAPS in the first round
- Use "Y" as suffix for those Instructions: MOVUPSYrr, ...
- All AVX instructions in X86InstrSSE.td will move soon to a new X86InstrAVX
  file.

llvm-svn: 107996
 2010-07-09 18:27:43 +00:00
Bruno Cardoso Lopes
144923dccf Merge VEX enums with other x86 enum forms. Also fix all checks of which VEX 
fields to use. 

llvm-svn: 107952
 2010-07-09 01:56:45 +00:00
Bruno Cardoso Lopes
a6bfda61b9 Factor out x86 segment override prefix encoding, and also use it for VEX 
llvm-svn: 107942
 2010-07-09 00:38:14 +00:00
Chris Lattner
fe434abafa reject pseudo instructions early in the encoder. 
llvm-svn: 107939
 2010-07-09 00:17:50 +00:00
Bruno Cardoso Lopes
f00a155876 Remove trailing whitespaces from file 
llvm-svn: 107937
 2010-07-09 00:07:19 +00:00
Chris Lattner
49ac65543c Change LEA to have 5 operands for its memory operand, just 
like all other instructions, even though a segment is not
allowed.  This resolves a bunch of gross hacks in the 
encoder and makes LEA more consistent with the rest of the
instruction set.

No functionality change.

llvm-svn: 107934
 2010-07-08 23:46:44 +00:00
Chris Lattner
18802e1a55 add some long-overdue enums to refer to the parts of the 5-operand 
X86 memory operand.

llvm-svn: 107925
 2010-07-08 22:41:28 +00:00
Chris Lattner
012d7537ee Rework segment prefix emission code to handle segments 
in memory operands at the same type as hard coded segments.
This fixes problems where we'd emit the segment override after
the REX prefix on instructions like:
mov %gs:(%rdi), %rax

This fixes rdar://8127102.  I have several cleanup patches coming
next.

llvm-svn: 107917
 2010-07-08 22:28:12 +00:00
Chris Lattner
155420f59f finish up support for callw: PR7195 
llvm-svn: 107826
 2010-07-07 22:35:13 +00:00
Chris Lattner
6a5db9c9c9 Implement the major chunk of PR7195: support for 'callw' 
in the integrated assembler.  Still some discussion to be
done.

llvm-svn: 107825
 2010-07-07 22:27:31 +00:00
Bruno Cardoso Lopes
af8968696a Fix comment from previous patch 
llvm-svn: 107717
 2010-07-06 22:38:32 +00:00
Bruno Cardoso Lopes
a0b37e839c Add AVX vblendvpd, vblendvps and vpblendvb instructions 
Update VEX encoding to support those new instructions

llvm-svn: 107715
 2010-07-06 22:36:24 +00:00
Chris Lattner
1e38d7d66d indentation 
llvm-svn: 107599
 2010-07-04 22:56:10 +00:00
Bruno Cardoso Lopes
4931e183b5 - Add support for the rest of AVX SSE3 instructions 
- Fix VEX prefix to be emitted with 3 bytes whenever VEX_5M
represents a REX equivalent two byte leading opcode

llvm-svn: 107523
 2010-07-02 22:06:54 +00:00
Bruno Cardoso Lopes
956316a3d7 - Add AVX SSE2 Move doubleword and quadword instructions. 
- Add encode bits for VEX_W
- All 128-bit SSE 1 & SSE2 instructions that are described
  in the .td file now have a AVX encoded form already working.

llvm-svn: 107365
 2010-07-01 01:20:06 +00:00
Bruno Cardoso Lopes
cfbebb3921 - Add AVX form of all SSE2 logical instructions 
- Add VEX encoding bits to x86 MRM0r-MRM7r

llvm-svn: 107238
 2010-06-30 01:58:37 +00:00
Bruno Cardoso Lopes
e1b05180de Add AVX ld/st XCSR register. 
Add VEX encoding bits for MRMXm x86 form

llvm-svn: 107204
 2010-06-29 20:35:48 +00:00
Bruno Cardoso Lopes
45109dd6c1 Reapply r106896: 
Add several AVX MOV flavors
Support VEX encoding for MRMDestReg

llvm-svn: 106912
 2010-06-25 23:33:42 +00:00
Bruno Cardoso Lopes
cc4c01f859 revert this now, it's using avx instead of sse :) 
llvm-svn: 106906
 2010-06-25 23:04:29 +00:00
Bruno Cardoso Lopes
04ac570a8d Add several AVX MOV flavors 
Support VEX encoding for MRMDestReg

llvm-svn: 106896
 2010-06-25 22:27:51 +00:00
Bruno Cardoso Lopes
11a236d970 - Add AVX COMI{SS,SD}{rr,rm} and UCOMI{SS,SD}{rr,rm}. 
- Fix a small VEX encoding issue.
- Move compare instructions to their appropriate place.

llvm-svn: 106787
 2010-06-24 20:48:23 +00:00
Bruno Cardoso Lopes
93ec8dcd01 Add AVX MOV{SS,SD}{rr,rm} instructions 
llvm-svn: 106588
 2010-06-22 22:38:56 +00:00
Chris Lattner
def4def8f9 rip out dead code. 
llvm-svn: 106365
 2010-06-19 00:34:14 +00:00
Chris Lattner
ed5a217085 fix rdar://7873482 by teaching the instruction encoder to emit 
segment prefixes.  Daniel wrote most of this patch.

llvm-svn: 106364
 2010-06-19 00:34:00 +00:00
Bruno Cardoso Lopes
df3435eb33 More AVX: {ADD,SUB,MUL,DIV}{PD,PS}rr 
Handle OpSize TSFlag for AVX

llvm-svn: 105869
 2010-06-12 01:23:26 +00:00
Bruno Cardoso Lopes
df2629b4db Add some comments about REX fields 
llvm-svn: 105860
 2010-06-12 00:03:52 +00:00
Bruno Cardoso Lopes
69141fd639 More AVX instructions ({ADD,SUB,MUL,DIV}{SS,SD}rm) 
Introduce the VEX_X field

llvm-svn: 105859
 2010-06-11 23:50:47 +00:00
Eric Christopher
3cb51e059d Split out these asserts so it's more apparent why we're not assembling 
that rip-relative address when executing in 32-bit mode.

llvm-svn: 105656
 2010-06-08 22:57:33 +00:00
Bruno Cardoso Lopes
255fda615d Reapply r105521, this time appending "LLU" to 64 bit 
immediates to avoid breaking the build.

llvm-svn: 105652
 2010-06-08 22:51:23 +00:00
Chris Lattner
33d0622cdc revert r105521, which is breaking the buildbots with stuff like this: 
In file included from X86InstrInfo.cpp:16:
X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type

llvm-svn: 105524
 2010-06-05 04:17:30 +00:00
Bruno Cardoso Lopes
b05131d907 Initial AVX support for some instructions. No patterns matched 
yet, only assembly encoding support.

llvm-svn: 105521
 2010-06-05 03:53:24 +00:00
Daniel Dunbar
7252b48af1 MCCodeEmitter: Add target independent fixup flag for is-pc-relative. 
llvm-svn: 98954
 2010-03-19 10:43:23 +00:00
Daniel Dunbar
1a50b05aff X86MCCodeEmitter: Fix two minor issues with reloc_riprel_4byte_movq_load, we 
were missing it on some movq instructions and were not including the appropriate
PCrel bias.

llvm-svn: 98880
 2010-03-18 21:53:54 +00:00
Chris Lattner
bf3e096258 fix an x86-64 encoding bug Daniel found. 
llvm-svn: 98855
 2010-03-18 20:04:36 +00:00
Chris Lattner
45ab55ccec add a special relocation type for movq loads for object 
files that produce special relocation types where the 
linker changes movq's into lea's.

llvm-svn: 98839
 2010-03-18 18:10:56 +00:00
Chris Lattner
b29b154904 make pcrel immediate values relative to the start of the field, 
not the end of the field, fixing rdar://7651978

llvm-svn: 96330
 2010-02-16 05:03:17 +00:00
Chris Lattner
b9c4a15ad5 teach the encoder to handle pseudo instructions like FP_REG_KILL, 
encoding them into nothing.

llvm-svn: 96110
 2010-02-13 19:16:53 +00:00
Daniel Dunbar
1581cae46f X86: Move extended MCFixupKinds into X86FixupKinds.h 
llvm-svn: 96088
 2010-02-13 09:27:52 +00:00
Chris Lattner
8530ba626c add encoder support and tests for rdtscp 
llvm-svn: 96076
 2010-02-13 03:42:24 +00:00
Chris Lattner
5b01ab848c remove special cases for vmlaunch, vmresume, vmxoff, and swapgs 
fix swapgs to be spelled right.

llvm-svn: 96058
 2010-02-13 00:41:14 +00:00
Chris Lattner
1d25e3978d Remove special cases for [LM]FENCE, MONITOR and MWAIT from 
encoder and decoder by using new MRM_ forms.

llvm-svn: 96048
 2010-02-12 23:54:57 +00:00
Chris Lattner
4170bb81da implement the rest of correct x86-64 encoder support for 
rip-relative addresses, and add a testcase.

llvm-svn: 96040
 2010-02-12 23:24:09 +00:00
Chris Lattner
946403d05f give MCCodeEmitters access to the current MCContext. 
llvm-svn: 96038
 2010-02-12 23:12:47 +00:00
Chris Lattner
e90d092fd7 implement infrastructure to support fixups for rip-rel 
addressing.  This isn't complete because I need an MCContext
to generate new MCExprs.

llvm-svn: 96036
 2010-02-12 23:00:36 +00:00
Chris Lattner
0a7654c7c9 pull the rip-relative addressing mode case up early. 
llvm-svn: 96031
 2010-02-12 22:47:55 +00:00
Chris Lattner
3df1321651 fixme resolved! 
llvm-svn: 96029
 2010-02-12 22:39:06 +00:00
Chris Lattner
1e01ac75bc start producing reloc_pcrel_4byte/reloc_pcrel_1byte for calls. 
llvm-svn: 96028
 2010-02-12 22:36:47 +00:00