Commit Graph

1609 Commits

Author SHA1 Message Date
David Goodwin
d0edce4c0d Restore the -post-RA-scheduler flag as an override for the target specification. Remove -mattr for setting PostRAScheduler enable and instead use CPU string.
llvm-svn: 83215
2009-10-01 21:46:35 +00:00
Evan Cheng
272a738580 ARM::tPOP and tPOP_RET each has an extra writeback operand now.
llvm-svn: 83214
2009-10-01 20:54:53 +00:00
Evan Cheng
241092d89f Add hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq flags to ld / st multiple,
ld / st pairs, etc.

llvm-svn: 83197
2009-10-01 08:22:27 +00:00
Evan Cheng
dc5ac208bf Update ARM JIT emitter to account for ld/st multiple changes.
llvm-svn: 83192
2009-10-01 01:39:21 +00:00
Evan Cheng
4dd7d7156e Change ld/st multiples to explicitly model the writeback to base register. This fixes most of the -ldstopti-before-sched2 regressions.
llvm-svn: 83191
2009-10-01 01:33:39 +00:00
Devang Patel
e097bf49d0 Use MachineInstr as an processDebugLoc() argument.
This will allow processDebugLoc() to handle scopes for DWARF debug info. 

llvm-svn: 83183
2009-09-30 23:12:50 +00:00
Bob Wilson
d6896006b1 Use OutStreamer.SwitchSection instead of writing out textual section directives.
Add a new TargetLoweringObjectFileMachO::getConstTextCoalSection method to
get access to that section.

llvm-svn: 83178
2009-09-30 22:25:37 +00:00
Bob Wilson
1cf44c8225 Add a new virtual EmitStartOfAsmFile method to the AsmPrinter and use this
to emit target-specific things at the beginning of the asm output.  This
fixes a problem for PPC, where the text sections are not being kept together
as expected.  The base class doInitialization code calls DW->BeginModule()
which emits a bunch of DWARF section directives.  The PPC doInitialization
code then emits all the TEXT section directives, with the intention that they
will be kept together. But as I understand it, the Darwin assembler treats
the default TEXT section as a special case and moves it to the beginning of
the file, which means that all those DWARF sections are in the middle of
the text.  With this change, the EmitStartOfAsmFile hook is called before
the DWARF section directives are emitted, so that all the PPC text section
directives come out right at the beginning of the file.

llvm-svn: 83176
2009-09-30 22:06:26 +00:00
Bob Wilson
233aa46c87 The AsmPrinter base class contains a DwarfWriter member, so there's no need
for derived AsmPrinters to add another one.  In some cases, fixing this
removes the need to override the doInitialization method.

llvm-svn: 83170
2009-09-30 21:24:45 +00:00
Jim Grosbach
2c211c7bfe Clarify comment phrasing.
llvm-svn: 83148
2009-09-30 15:23:38 +00:00
Evan Cheng
86bd5c3ae1 Add a option which would move ld/st multiple pass before post-alloc scheduling.
llvm-svn: 83145
2009-09-30 08:53:01 +00:00
Jim Grosbach
9655673c95 When checking whether we need to reserve a register for the scavenger,
the size of the saved frame pointer needs to be taken into account.

llvm-svn: 83136
2009-09-30 01:43:29 +00:00
Jim Grosbach
2d057f09e8 Add "isBarrier = 1" to return instructions.
Patch by Sylvere Teissier.

llvm-svn: 83135
2009-09-30 01:35:11 +00:00
Bob Wilson
48f9855607 For Darwin, emit all the text section directives together before the dwarf
section directives.  This causes the assembler to put the text sections at
the beginning of the object file, which helps work around a limitation of the
Darwin ARM relocations.  Radar 7255355.

llvm-svn: 83127
2009-09-30 00:23:42 +00:00
David Goodwin
a282690f82 Remove -post-RA-schedule flag and add a TargetSubtarget method to enable post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8.
llvm-svn: 83122
2009-09-30 00:10:16 +00:00
Jim Grosbach
278d0d5b3d minor cleanup and add clarifying comment
llvm-svn: 83117
2009-09-29 23:17:20 +00:00
Evan Cheng
d2bf81c7af Fix PR4687. Pre ARMv5te does not support ldrd / strd. Patch by John Tytgat.
llvm-svn: 83058
2009-09-29 07:07:30 +00:00
Jim Grosbach
9cb82ce219 Adjust processFunctionBeforeCalleeSavedScan() to correctly reserve a stack
slot for the register scavenger when compiling Thumb1 functions.

llvm-svn: 83023
2009-09-28 22:08:06 +00:00
Evan Cheng
c15ba1de94 Fix Thumb2 IT block pass bug. t2MOVi32imm may not be the start of a IT block.
llvm-svn: 83008
2009-09-28 20:47:15 +00:00
Jakob Stoklund Olesen
31fcbdefbb Introduce the TargetInstrInfo::KILL machine instruction and get rid of the
unused DECLARE instruction.

KILL is not yet used anywhere, it will replace TargetInstrInfo::IMPLICIT_DEF
in the places where IMPLICIT_DEF is just used to alter liveness of physical
registers.

llvm-svn: 83006
2009-09-28 20:32:26 +00:00
Bob Wilson
bbcf30c05c Pass the optimization level when constructing the ARM instruction selector.
Otherwise, it is always set to "default", which prevents debug info from
even being generated during isel.  Radar 7250345.

llvm-svn: 82988
2009-09-28 14:30:20 +00:00
Evan Cheng
54a1a87862 Make ARM and Thumb2 32-bit immediate materialization into a single 32-bit pseudo
instruction. This makes it re-materializable.

Thumb2 will split it back out into two instructions so IT pass will generate the
right mask. Also, this expose opportunies to optimize the movw to a 16-bit move.

llvm-svn: 82982
2009-09-28 09:14:39 +00:00
Anton Korobeynikov
2e54b03741 Fix thinko in my recent movt commit: it's not safe to remat movt, since it has input reg argument.
Disable rematting of it for now.

llvm-svn: 82975
2009-09-28 07:26:46 +00:00
Anton Korobeynikov
189ce11684 Use movt/movw pair to materialize 32 bit constants on ARMv6T2+.
This should be better than single load from constpool.

llvm-svn: 82948
2009-09-27 23:52:58 +00:00
Evan Cheng
ffe6da0734 Enable pre-regalloc load / store multiple pass for Thumb2.
llvm-svn: 82893
2009-09-27 09:46:04 +00:00
Evan Cheng
48479d0c8f Really remove this option.
llvm-svn: 82838
2009-09-26 02:49:49 +00:00
Evan Cheng
1088c37212 Remove a couple of unused command line options.
llvm-svn: 82837
2009-09-26 02:45:45 +00:00
Evan Cheng
c4e3168b65 Add comment.
llvm-svn: 82836
2009-09-26 02:43:36 +00:00
Anton Korobeynikov
35078c311e Regenerate
llvm-svn: 82814
2009-09-25 22:53:17 +00:00
Evan Cheng
c0edc5ee28 Code clean up and prepare for Thumb2 support. No functionality changes.
llvm-svn: 82805
2009-09-25 21:44:53 +00:00
Dan Gohman
0ac693a89e Improve MachineMemOperand handling.
- Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions.
   This eliminates MachineInstr's std::list member and allows the data to be
   created by isel and live for the remainder of codegen, avoiding a lot of
   copying and unnecessary translation. This also shrinks MemSDNode.
 - Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated
   fields for MachineMemOperands.
 - Change MemSDNode to have a MachineMemOperand member instead of its own
   fields with the same information. This introduces some redundancy, but
   it's more consistent with what MachineInstr will eventually want.
 - Ignore alignment when searching for redundant loads for CSE, but remember
   the greatest alignment.

Target-specific code which previously used MemOperandSDNodes with generic
SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range
so that the SelectionDAG framework knows that MachineMemOperand information
is available.

llvm-svn: 82794
2009-09-25 20:36:54 +00:00
Dan Gohman
0c4e55a2f8 Rename getTargetNode to getMachineNode, for consistency with the
naming scheme used in SelectionDAG, where there are multiple kinds
of "target" nodes, but "machine" nodes are nodes which represent
a MachineInstr.

llvm-svn: 82790
2009-09-25 18:54:59 +00:00
David Goodwin
89f5854ddd Finish scheduling itineraries for NEON.
llvm-svn: 82788
2009-09-25 18:38:29 +00:00
Bob Wilson
c5784025af Add some comments to clarify things that I discovered this week.
llvm-svn: 82773
2009-09-25 16:34:46 +00:00
Bob Wilson
94e29af5ac pr4926: ARM requires the stack pointer to be aligned, even for leaf functions.
For the AAPCS ABI, SP must always be 4-byte aligned, and at any "public
interface" it must be 8-byte aligned.  For the older ARM APCS ABI, the stack
alignment is just always 4 bytes.  For X86, we currently align SP at
entry to a function (e.g., to 16 bytes for Darwin), but no stack alignment
is needed at other times, such as for a leaf function.

After discussing this with Dan, I decided to go with the approach of adding
a new "TransientStackAlignment" field to TargetFrameInfo.  This value
specifies the stack alignment that must be maintained even in between calls.
It defaults to 1 except for ARM, where it is 4.  (Some other targets may
also want to set this if they have similar stack requirements. It's not
currently required for PPC because it sets targetHandlesStackFrameRounding
and handles the alignment in target-specific code.) The existing StackAlignment
value specifies the alignment upon entry to a function, which is how we've
been using it anyway.

llvm-svn: 82767
2009-09-25 14:41:49 +00:00
Jim Grosbach
3d527ff081 Start of revamping the register scavenging in PEI. ARM Thumb1 is the driving
interest for this, as it currently reserves a register rather than using
the scavenger for matierializing constants as needed.

Instead of scavenging registers on the fly while eliminating frame indices,
new virtual registers are created, and then a scavenged collectively in a
post-pass over the function. This isolates the bits that need to interact
with the scavenger, and sets the stage for more intelligent use, and reuse,
of scavenged registers.

For the time being, this is disabled by default. Once the bugs are worked out,
the current scavenging calls in replaceFrameIndices() will be removed and
the post-pass scavenging will be the default. Until then,
-enable-frame-index-scavenging enables the new code. Currently, only the
Thumb1 back end is set up to use it.

llvm-svn: 82734
2009-09-24 23:52:18 +00:00
David Goodwin
3ac3dcacc7 Make the end-of-itinerary mark explicit. Some cleanup.
llvm-svn: 82709
2009-09-24 20:22:50 +00:00
David Goodwin
1d72b88015 Checkpoint NEON scheduling itineraries.
llvm-svn: 82657
2009-09-23 21:38:08 +00:00
Anton Korobeynikov
829a3a18d2 ARM does not support offset folding (yet). Disable it for now.
This fixes PR5031. Unfortunately, there is no small testcase :(

llvm-svn: 82643
2009-09-23 19:04:09 +00:00
David Goodwin
0db84be1dc Add Cortex-A8 VFP model.
llvm-svn: 82483
2009-09-21 20:52:17 +00:00
Daniel Dunbar
db16b2c6bb Register the MachineModuleInfo for the ARM JIT, and update JITDwarfEmitter to
assert if the setModuleInfo hasn't been called.

llvm-svn: 82441
2009-09-21 05:58:35 +00:00
Evan Cheng
7714c8412d Fix PR4926. When target hook EmitInstrWithCustomInserter() insert new basic blocks and update CFG, it should also inform sdisel of the changes so the phi source operands will come from the right basic blocks.
llvm-svn: 82311
2009-09-19 09:51:03 +00:00
Bob Wilson
1b311a6a9b Fix a typo in an assertion message.
llvm-svn: 82284
2009-09-18 21:42:44 +00:00
Evan Cheng
7cb9c456e5 Enhance EmitInstrWithCustomInserter() so target can specify CFG changes that sdisel will use to properly complete phi nodes.
Not functionality change yet.

llvm-svn: 82273
2009-09-18 21:02:19 +00:00
Bob Wilson
989568d935 Expand vector floating-point conversions not supported by NEON.
llvm-svn: 82074
2009-09-16 20:20:44 +00:00
Bob Wilson
8770c809c2 Expand some more vector operations not supported by Neon.
llvm-svn: 81969
2009-09-16 00:32:15 +00:00
Bob Wilson
c01a94dad0 Neon does not support vector divide or remainder. Expand them.
llvm-svn: 81966
2009-09-16 00:17:28 +00:00
Bob Wilson
f091792f40 Expand all v2f64 arithmetic operations for Neon.
Radar 7200803.  (This should also fix the
SingleSource/UnitTests/Vector/sumarray-dbl test.)

llvm-svn: 81959
2009-09-15 23:55:57 +00:00
Bob Wilson
a42ff3190c Handle AddrMode4 for Thumb2 in rewriteT2FrameIndex. This occurs for
VLDM/VSTM instructions, and without this check, the code assumes that an
offset is allowed, as it would be with VLDR/VSTR.  The asm printer,
however, silently drops the offset, producing incorrect code.  Since the
address register in this case is either the stack or frame pointer, the
spill location ends up conflicting with some other stack slot or with
outgoing arguments on the stack.

llvm-svn: 81879
2009-09-15 17:56:18 +00:00
Sandeep Patel
7727a68464 Fix superreg use in ARMAsmPrinter. Approved by Anton Korobeynikov.
llvm-svn: 81878
2009-09-15 17:53:11 +00:00