1976 Commits

Author SHA1 Message Date
Jim Grosbach
02bf78f5ca ARM BL/BLX instruction fixups should use relocations.
We on the linker to resolve calls to the appropriate BL/BLX instruction
to make interworking function correctly. It uses the symbol in the
relocation to do that, so we need to be careful about being too clever.

To enable this for ARM mode, split the BL/BLX fixup kind off from the
unconditional-branch fixups.

rdar://10927209

llvm-svn: 151571
2012-02-27 21:36:23 +00:00
Craig Topper
ab46706aa9 X86 disassembler support for jcxz, jecxz, and jrcxz. Fixes PR11643. Patch by Kay Tiong Khoo.
llvm-svn: 151510
2012-02-27 01:54:29 +00:00
Michael J. Spencer
ba986d585c Emit global ctors into .CRT$XCU instead of .ctors on Win32. Patch by Joe Groff!
llvm-svn: 151289
2012-02-23 21:56:08 +00:00
Kevin Enderby
4e089c2b5b Updated the llvm-mc disassembler C API to support for the X86 target.
rdar://10873652

As part of this I updated the llvm-mc disassembler C API to always call the
SymbolLookUp call back even if there is no getOpInfo call back.  If there is a
getOpInfo call back that is tried first and then if that gets no information
then the  SymbolLookUp is called.  I also made the code more robust by
memset(3)'ing to zero the LLVMOpInfo1 struct before then setting
SymbolicOp.Value before for the call to getOpInfo.  And also don't use any
values from the  LLVMOpInfo1 struct if getOpInfo returns 0.  And also don't
use any of the ReferenceType or ReferenceName values from SymbolLookUp if it
returns NULL. rdar://10873563 and rdar://10873683

For the X86 target also fixed bugs so the annotations get printed. 

Also fixed a few places in the ARM target that was not producing symbolic
operands for some instructions.  rdar://10878166

llvm-svn: 151267
2012-02-23 18:18:17 +00:00
Craig Topper
cfbfa3dcd1 Add vmfunc instruction to X86 assembler and disassembler.
llvm-svn: 150899
2012-02-19 01:39:49 +00:00
Craig Topper
ecf21d8132 Add X86 assembler and disassembler support for AMD SVM instructions. Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication.
llvm-svn: 150873
2012-02-18 08:19:49 +00:00
Eli Bendersky
4afdeeb682 Replace all instances of dg.exp file with lit.local.cfg, since all tests are run with LIT now and now Dejagnu. dg.exp is no longer needed.
Patch reviewed by Daniel Dunbar. It will be followed by additional cleanup patches.

llvm-svn: 150664
2012-02-16 06:28:33 +00:00
David Meyer
ce969dfbf0 For ELF, also call fixSymbolsInTLSFixups() on expressions passed to EmitValue (literal values). Previously only called on expressions in instructions. New test cases added to tls.s, tls-i386.s. Resolves PR11981.
llvm-svn: 150582
2012-02-15 15:09:06 +00:00
James Molloy
85be8f7f88 Teach the MC and disassembler about SoftFail, and hook it up to UNPREDICTABLE on ARM. Wire this to tBLX in order to provide test coverage.
llvm-svn: 150169
2012-02-09 10:56:31 +00:00
Kevin Enderby
cb876a7560 Fixed a crash in llvm-mc for Mach-O when a symbol difference expression uses a
symbol from an assignment.  In this case the symbol did not have a fragment so
MCObjectWriter::IsSymbolRefDifferenceFullyResolved() should not have been
calling IsSymbolRefDifferenceFullyResolvedImpl() with a NULL fragment and should
just have returned false in that case.

llvm-svn: 149442
2012-01-31 23:02:57 +00:00
Devang Patel
be1817e3e0 Intel syntax. Adjust special code, used to recognize cmp<comparison code>{ss,sd,ps,pd}, for intel syntax.
llvm-svn: 149291
2012-01-30 22:47:12 +00:00
Devang Patel
a5bfdedb9f Intel syntax. Support .intel_syntax directive.
llvm-svn: 149270
2012-01-30 20:02:42 +00:00
James Molloy
b586b7c9c7 Ensure .AliasedSymbol() is called on all uses of getSymbol(). Affects ARM and MIPS ELF backends.
Fixes PR11877

llvm-svn: 149180
2012-01-28 15:58:32 +00:00
Rafael Espindola
c74f450f77 Small improvement to the recursion detection logic from the previous commit.
llvm-svn: 149175
2012-01-28 06:22:14 +00:00
Rafael Espindola
82e15e4544 Handle recursive variable definitions directly. This gives us better error
messages and allows us to fix PR11865.

llvm-svn: 149174
2012-01-28 05:57:00 +00:00
Devang Patel
e4725ba181 Intel Syntax: Parse mem operand with seg reg. QWORD PTR FS:[320]
llvm-svn: 149142
2012-01-27 19:48:28 +00:00
James Molloy
402abeda73 Add support for the R_ARM_TARGET1 relocation, which should be given to relocations applied to all C++ constructors and destructors.
This enables the linker to match concrete relocation types (absolute or relative) with whatever library or C++ support code is being linked against.

llvm-svn: 149057
2012-01-26 09:25:43 +00:00
Jim Grosbach
20a6580dff ARM assemly parsing and validation of IT instruction.
"Although a Thumb2 instruction, the IT mnemonic shall be permitted in
ARM mode, and the condition verified to match the condition code(s)
on the following instruction(s)."

PR11853

llvm-svn: 148969
2012-01-25 19:52:01 +00:00
Jim Grosbach
e8095f3b49 NEON VLD4(all lanes) assembly parsing and encoding.
llvm-svn: 148884
2012-01-25 00:01:08 +00:00
Jim Grosbach
f478b2a706 NEON VLD3(all lanes) assembly parsing and encoding.
llvm-svn: 148882
2012-01-24 23:47:04 +00:00
Jim Grosbach
012239e10a ARM Darwin symbol ref differences w/o subsection-via-symbols.
When not using subsections via symbols, the assembler can resolve
symbol differences (including pcrel references) to non-local
labels at assembly time, not just those in the same atom.

llvm-svn: 148865
2012-01-24 21:45:25 +00:00
Devang Patel
0da753c9e6 Intel Syntax: Extend special hand coded logic, to recognize special instructions, for intel syntax.
llvm-svn: 148864
2012-01-24 21:43:36 +00:00
Jim Grosbach
e151b15949 NEON VST4(one lane) assembly parsing and encoding.
llvm-svn: 148836
2012-01-24 18:53:13 +00:00
Jim Grosbach
a78348fcda NEON VLD4(one lane) assembly parsing and encoding.
llvm-svn: 148832
2012-01-24 18:37:25 +00:00
Jim Grosbach
f3607eac5d NEON Two-operand assembly aliases for VSRA.
llvm-svn: 148821
2012-01-24 17:55:36 +00:00
Jim Grosbach
47f7ce80b8 Remove redundant test file.
llvm-svn: 148820
2012-01-24 17:55:32 +00:00
Jim Grosbach
630dd380c7 NEON Two-operand assembly aliases for VSLI.
llvm-svn: 148819
2012-01-24 17:49:15 +00:00
Jim Grosbach
42c0f99aa0 NEON Two-operand assembly aliases for VSRI.
llvm-svn: 148818
2012-01-24 17:46:58 +00:00
Jim Grosbach
703b0bb646 Tidy up.
llvm-svn: 148817
2012-01-24 17:46:54 +00:00
Jim Grosbach
3be662b372 NEON VST4(multiple 4 element structures) assembly parsing.
llvm-svn: 148764
2012-01-24 00:58:13 +00:00
Jim Grosbach
ca32a49eb5 NEON VLD4(multiple 4 element structures) assembly parsing.
llvm-svn: 148762
2012-01-24 00:43:17 +00:00
Jim Grosbach
a4687dcf5a NEON VST3(single element from one lane) assembly parsing.
llvm-svn: 148755
2012-01-24 00:07:41 +00:00
Jim Grosbach
048162ddf9 NEON VST3(multiple 3-element structures) assembly parsing.
llvm-svn: 148748
2012-01-23 23:45:44 +00:00
Jim Grosbach
8035fac461 NEON VLD3(multiple 3-element structures) assembly parsing.
llvm-svn: 148745
2012-01-23 23:20:46 +00:00
Devang Patel
327773a25b Intel syntax: Robustify parsing of memory operand's displacement experssion.
llvm-svn: 148737
2012-01-23 22:35:25 +00:00
Jim Grosbach
dd667a11d3 NEON VLD3 lane-indexed assembly parsing and encoding.
llvm-svn: 148734
2012-01-23 21:53:26 +00:00
Rafael Espindola
9f3a003d3c Add support for .cfi_signal_frame. Fixes pr11762.
llvm-svn: 148733
2012-01-23 21:51:52 +00:00
Devang Patel
3c6289f43a Intel syntax: Parse memory operand with empty base reg, e.g. DWORD PTR [4*RDI]
llvm-svn: 148721
2012-01-23 20:20:06 +00:00
Jim Grosbach
0eeacbfe2e Simplify some NEON assembly pseudo definitions.
Let the generic token alias definitions handle the data subtype
suffices. We don't need explicit versions for each.

llvm-svn: 148718
2012-01-23 19:39:08 +00:00
Devang Patel
9698de5bf3 Intel syntax: Parse segment registers.
llvm-svn: 148712
2012-01-23 18:31:58 +00:00
Devang Patel
0ecda3fc14 Intel syntax: Robustify register parsing.
llvm-svn: 148591
2012-01-20 22:32:05 +00:00
Devang Patel
0638a44a24 Intel syntax: Parse ... PTR [-8]
llvm-svn: 148570
2012-01-20 21:21:01 +00:00
Devang Patel
e836c95860 Intel syntax: For now, disable ambiguous JMP64pcrel32 for intel syntax.
llvm-svn: 148569
2012-01-20 21:14:06 +00:00
Jim Grosbach
4579f05f36 NEON use vmov.i32 to splat some f32 values into vectors.
For bit patterns that aren't representable using the 8-bit floating point
representation for vmov.f32, but are representable via vmov.i32, treat
the .f32 syntax as an alias. Most importantly, this covers the case
'vmov.f32 Vd, #0.0'.

rdar://10616677

llvm-svn: 148556
2012-01-20 18:09:51 +00:00
Devang Patel
b42cea31aa Post process 'and', 'sub' instructions and select better encoding, if available.
llvm-svn: 148489
2012-01-19 18:40:55 +00:00
Devang Patel
27ef211648 Intel syntax: There is no need to create unary expr for simple negative displacement.
llvm-svn: 148486
2012-01-19 18:15:51 +00:00
Devang Patel
999eaa4b85 Post process 'xor', 'or' and 'cmp' instructions and select better encoding, if available.
llvm-svn: 148485
2012-01-19 17:53:25 +00:00
Jim Grosbach
48afa48c3e Add testcase.
llvm-svn: 148454
2012-01-19 01:36:59 +00:00
Jim Grosbach
b7ab9edb4e Thumb2 alternate syntax for LDR(literal) and friends.
Explicit pc-relative syntax. For example, "ldrb r2, [pc, #-22]".

rdar://10250964

llvm-svn: 148432
2012-01-18 22:46:46 +00:00
Devang Patel
ee49d825b1 Process instructions after match to select alternative encoding which may be more desirable.
llvm-svn: 148431
2012-01-18 22:42:29 +00:00