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Author SHA1 Message Date
Bill Wendling
127dd6052c Add lld to projects to tag. 
llvm-svn: 195102
 2013-11-19 04:58:46 +00:00
Daniel Jasper
9d3984a876 Add .clang-format without column limit to subdirectory tests/. 
A column limit in the test folder can lead to trouble as the RUN, CHECK,
etc. comments can potentially be broken over multiple lines changing
their meaning. Without column limit, clang-format will simply keep the
test author's line breaks.

llvm-svn: 195100
 2013-11-19 04:26:05 +00:00
Andrew Trick
9f7d826e8a Use symbolic operands in the patchpoint folding routine and fix a spilling bug. 
Fixes <rdar://15487687> [JS] AnyRegCC argument ends up being spilled

llvm-svn: 195094
 2013-11-19 03:29:59 +00:00
Andrew Trick
15aac659a7 Add an abstraction to handle patchpoint operands. 
Hard-coded operand indices were scattered throughout lowering stages
and layers. It was super bug prone.

llvm-svn: 195093
 2013-11-19 03:29:56 +00:00
Juergen Ributzka
990c8318f8 [weak vtables] Place class definitions into anonymous namespaces to prevent weak vtables. 
This patch places class definitions in implementation files into anonymous
namespaces to prevent weak vtables. This eliminates the need of providing an
out-of-line definition to pin the vtable explicitly to the file.

llvm-svn: 195092
 2013-11-19 03:08:35 +00:00
Hao Liu
b26dfe0306 Implement AArch64 neon instructions class SIMD lsone and SIMD lone-post. 
llvm-svn: 195078
 2013-11-19 02:17:05 +00:00
Eric Christopher
106d6557a8 Remove unused special member functions and reformat. 
llvm-svn: 195077
 2013-11-19 02:01:07 +00:00
Eric Christopher
51aecac48c Fix previous commit and fully remove variable. 
llvm-svn: 195076
 2013-11-19 01:52:38 +00:00
Eric Christopher
0d2c47bfb4 Remove unused variable. 
llvm-svn: 195075
 2013-11-19 01:50:29 +00:00
Jiangning Liu
42b7a215f4 Implement AArch64 SISD intrinsics for vget_high and vget_low. 
llvm-svn: 195074
 2013-11-19 01:46:48 +00:00
Kevin Qin
7b74269765 implement MC layer of AArch64 neon instruction PMULL and PMULL2 with 128 bit integer. 
llvm-svn: 195072
 2013-11-19 01:40:25 +00:00
Jiangning Liu
7c858f236d Add predicate for AArch64 crypto instructions. 
llvm-svn: 195071
 2013-11-19 01:38:31 +00:00
Jack Carter
8bb31d387d [Mips] Support for MicroMips STO refactoring. 
No true functional changes.

Change the "hack" name of emitMipsHackSTOCG to emitSymSTO.

Remove demonstration code in AsmParser for emitMipsHackSTOCG and
emitMipsHackELFFlags. The STO field is in an ELF symbol and is not
an explicit directive. That said, we are missing the compliment call
in AsmParser and that will need to be addressed soon.

XFAIL dummy tests for emitMipsHackELFFlags and emitMipsHackELFFlags.
These will built out with following patches.

llvm-svn: 195067
 2013-11-19 01:25:18 +00:00
Juergen Ributzka
5357a6d64b [weak vtables] Remove a bunch of weak vtables 
This patch removes most of the trivial cases of weak vtables by pinning them to
a single object file. The memory leaks in this version have been fixed. Thanks
Alexey for pointing them out.

Differential Revision: http://llvm-reviews.chandlerc.com/D2068

Reviewed by Andy

llvm-svn: 195064
 2013-11-19 00:57:56 +00:00
David Blaikie
97d9c49ba1 llvm-dwarfdump: support for emitting only the debug_types section using -debug-dump 
llvm-svn: 195063
 2013-11-19 00:29:42 +00:00
David Blaikie
f941cd8a75 DwarfDebug: Move trailing else to the same line as prior closing brace 
llvm-svn: 195060
 2013-11-18 23:59:04 +00:00
David Blaikie
0fc401fb8f DwarfDebug: Remove some more redundant explicit constructions. 
llvm-svn: 195059
 2013-11-18 23:57:26 +00:00
Jack Carter
4091753064 [Mips] MipsTargetStreamer refactoring. 
No functionality changes.

llvm-svn: 195057
 2013-11-18 23:55:27 +00:00
David Blaikie
f1abd8ad9c DebugInfo: Simplify a few more explicit constructions, underconstrained types, and make DIType(MDNode*) explicit like all the other DI* node ctors. 
llvm-svn: 195055
 2013-11-18 23:33:32 +00:00
Reid Kleckner
552118c34a Revert "COFF: Emit all MCSymbols rather than filtering out some of them" 
This reverts commit r190888, to fix PR17967.  The original change wasn't
the right way to get @feat.00 into the object file.  The right fix is to
make @feat.00 be a global symbol.

llvm-svn: 195053
 2013-11-18 23:08:12 +00:00
Adrian Prantl
afeac86924 Debug info: Let LowerDbgDeclare perfom the dbg.declare -> dbg.value 
lowering only for load/stores to scalar allocas. The resulting values
confuse the backend and don't add anything because we can describe
array-allocas with a dbg.declare intrinsic just fine.

rdar://problem/15464571

llvm-svn: 195052
 2013-11-18 23:04:38 +00:00
Ahmed Bougacha
bd4c7e426e Docs: tweak code-block spacing. 
llvm-svn: 195049
 2013-11-18 22:26:59 +00:00
Paul Robinson
27ef03dc70 The 'optnone' attribute means don't inline anything into this function 
(except functions marked always_inline).
Functions with 'optnone' must also have 'noinline' so they don't get
inlined into any other function.

Based on work by Andrea Di Biagio.

llvm-svn: 195046
 2013-11-18 21:44:03 +00:00
Matt Arsenault
be108f1643 R600/SI: Fix moveToVALU when the first operand is VSrc. 
Moving into a VSrc doesn't always work, since it could be
replaced with an SGPR later.

llvm-svn: 195042
 2013-11-18 20:09:55 +00:00
Matt Arsenault
cdea5c8fe0 R600/SI: Fix multiple SGPR reads when using VCC. 
No other SGPR operands are allowed, so if VCC is
used, move the other to a VGPR.

llvm-svn: 195041
 2013-11-18 20:09:50 +00:00
Matt Arsenault
485f69c9cf R600/SI: Implement add i64, but do not yet enable. 
Test doesn't actually check the output. I need
to fix add i64 being matched for the addressing
calculations.

llvm-svn: 195040
 2013-11-18 20:09:47 +00:00
Matt Arsenault
2b3d70daa8 R600/SI: Specify SSrc operands 
llvm-svn: 195039
 2013-11-18 20:09:43 +00:00
Matt Arsenault
1e729e94db R600/SI: addc / adde i32 are legal 
llvm-svn: 195038
 2013-11-18 20:09:40 +00:00
Matt Arsenault
adcc6666c5 R600/SI: Match addc to S_ADD_U32. 
The carry always goes to SCC.

llvm-svn: 195037
 2013-11-18 20:09:37 +00:00
Matt Arsenault
3ce3089446 R600/SI: Match adde/sube to S_ADDC_U32/S_SUBB_U32 
llvm-svn: 195036
 2013-11-18 20:09:34 +00:00
Matt Arsenault
7202effe49 R600/SI: Specify S_ADD/S_SUB set SCC and add is commutable 
llvm-svn: 195035
 2013-11-18 20:09:32 +00:00
Matt Arsenault
62a8d8b89a R600/SI: Move patterns to match add / sub to scalar instructions 
llvm-svn: 195034
 2013-11-18 20:09:29 +00:00
Matt Arsenault
70b306fc07 R600/SI: Fix extra defs of VCC / SCC. 
When replacing scalar operations with vector,
the wrong implicit output register was used.

llvm-svn: 195033
 2013-11-18 20:09:21 +00:00
Tom Stellard
84bb236e61 R600: Enable the IR structurizer by default 
llvm-svn: 195031
 2013-11-18 19:43:44 +00:00
Tom Stellard
f1b1fa4727 R600: Fix a crash in the AMDILCFGStrucurizer 
The ifPatternMatch() function was not correctly reporting the number
of matches in some cases.

llvm-svn: 195030
 2013-11-18 19:43:38 +00:00
Tom Stellard
b3bf286ada R600: Add a SubtargetFeatture for disabling the ifcvt pass. 
This is useful when writing test cases for the AMDIL structurizer.

llvm-svn: 195029
 2013-11-18 19:43:33 +00:00
Tom Stellard
c6a94af8d4 R600: Use lower-case for EnableIRStructurizer feature 
llc converts all values passed to -mattr= to lowercase, so this
enables us to toggle this feature when using llc.

llvm-svn: 195028
 2013-11-18 19:43:29 +00:00
Tom Stellard
d0cdc72805 R600/SI: Fix illegal VGPR->SGPR copy inside of loop 
llvm-svn: 195026
 2013-11-18 18:50:20 +00:00
Tom Stellard
47634da2de R600/SI: Fix another case of illegal VGPR->SGPR copy 
llvm-svn: 195025
 2013-11-18 18:50:15 +00:00
Aaron Ballman
b8b01d327f Checking for a return value with FormatMessage; if the call fails, there's no guarantee that the buffer will be non-null. 
llvm-svn: 195019
 2013-11-18 17:43:22 +00:00
Aaron Ballman
fe287f3b35 Fixing a possible memory leak from a failing realloc() call. 
llvm-svn: 195018
 2013-11-18 17:33:32 +00:00
Alexander Kornienko
d817824d74 Recover gracefully when deserializing invalid YAML input. 
Fixes http://llvm.org/PR16221, http://llvm.org/PR15927
Phabricator: http://llvm-reviews.chandlerc.com/D1236

Patch by Andrew Tulloch!

llvm-svn: 195016
 2013-11-18 15:50:04 +00:00
Alexey Samsonov
cbf7462c74 [ASan] Fix PR17867 - make sure ASan doesn't crash if use-after-scope and use-after-return are combined. 
llvm-svn: 195014
 2013-11-18 14:53:55 +00:00
NAKAMURA Takumi
f5722be30d [PR17978] Mark two ARM/fast-isel tests as XFAIL:vg_leak due to GV. 
llvm-svn: 195010
 2013-11-18 13:50:19 +00:00
Arnold Schwaighofer
e4280ec4dd LoopVectorizer: Extend the induction variable to a larger type 
In some case the loop exit count computation can overflow. Extend the type to
prevent most of those cases.

The problem is loops like:
int main ()
{
  int a = 1;
  char b = 0;
  lbl:
    a &= 4;
    b--;
    if (b) goto lbl;
  return a;
}

The backedge count is 255. The induction variable type is i8. If we add one to
255 to get the exit count we overflow to zero.

To work around this issue we extend the type of the induction variable to i32 in
the case of i8 and i16.

PR17532

llvm-svn: 195008
 2013-11-18 13:14:32 +00:00
Daniel Sanders
52b1c62a95 [mips] Fix 'ran out of registers' in MIPS32 with FP64 when generating code for (ConstantFP 0.0) 
Fixed an inappropriate use of BuildPairF64 when compiling for MIPS32 with FP64
which resulted in an impossible constraint on the register allocation. It now
uses BuildPairF64_64.

llvm-svn: 195007
 2013-11-18 13:12:43 +00:00
Matheus Almeida
a941fd6ccd [mips][msa] Update encoding of bnz.v (typo). 
Note that there's no hardware yet that relies on that encoding.

llvm-svn: 195006
 2013-11-18 13:09:54 +00:00
Matheus Almeida
f3405464c6 [mips][msa] Fix immediate value of LSA instruction as it was being wrongly encoded. 
The immediate field should be encoded as "imm - 1" as the CPU always adds one to that field.

llvm-svn: 195004
 2013-11-18 12:32:49 +00:00
Alexey Samsonov
22aed953fb Fix forgotten member initialization detected by MSan bootstrap bot 
llvm-svn: 195003
 2013-11-18 11:06:01 +00:00
Daniel Sanders
4826d2b987 [mips][msa] Add MSA to the release notes. 
llvm-svn: 195001
 2013-11-18 10:38:47 +00:00