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Author SHA1 Message Date
Dan Gohman
e26025ddd0 When rotating loops, put the original header at the bottom of the 
loop, making the resulting loop significantly less ugly.  Also, zap
its trivial PHI nodes, since it's easy.

llvm-svn: 111255
 2010-08-17 17:39:21 +00:00
Bob Wilson
e382fce916 Change ARM PKHTB and PKHBT instructions to use a shift_imm operand to avoid 
printing "lsl #0".  This fixes the remaining parts of pr7792.  Make
corresponding changes for encoding/decoding these instructions.

llvm-svn: 111251
 2010-08-17 17:23:19 +00:00
Bob Wilson
6239dc42c6 Allow more cases of undef shuffle indices and add tests for them. 
llvm-svn: 111226
 2010-08-17 05:54:34 +00:00
Evan Cheng
0163d059e4 PHI elimination should not break back edge. It can cause some significant code placement issues. rdar://8263994 
good:
LBB0_2:
  mov     r2, r0
  . . .
  mov     r1, r2
  bne     LBB0_2

bad:
LBB0_2:
  mov     r2, r0
  . . .
@ BB#3:
  mov     r1, r2
  b       LBB0_2

llvm-svn: 111221
 2010-08-17 01:20:36 +00:00
Bob Wilson
2c5e6a9214 Add a testcase for svn 111208. 
llvm-svn: 111212
 2010-08-16 23:44:29 +00:00
Bob Wilson
d662e8cd02 Generalize a pattern for PKHTB: an SRL of 16-31 bits will guarantee 
that the high halfword is zero.  The shift need not be exactly 16 bits.

llvm-svn: 111196
 2010-08-16 22:26:55 +00:00
Bob Wilson
b776a55df5 Convert test to FileCheck. 
llvm-svn: 111195
 2010-08-16 22:21:13 +00:00
Bob Wilson
f174416619 Convert a test to use FileCheck. 
llvm-svn: 111153
 2010-08-16 17:05:27 +00:00
Dan Gohman
9178d0792f Instead, teach SimplifyCFG to trim non-address-taken blocks from 
indirectbr destination lists.

llvm-svn: 111122
 2010-08-16 14:41:14 +00:00
Dan Gohman
8ed4d1646e Revert r111058, the lint check for indirectbr successors that aren't 
address-taken. This can occur normally, if the code which took the
address got DCEd.

llvm-svn: 111121
 2010-08-16 14:39:19 +00:00
Benjamin Kramer
0224854fdc Test expects SSE, give him SSE. 
llvm-svn: 111115
 2010-08-15 23:32:03 +00:00
Benjamin Kramer
3116e6f58d Restore arch on these test, they fail on arm. 
llvm-svn: 111109
 2010-08-15 20:42:56 +00:00
Dale Johannesen
6e5cf0f5b6 Mark as XFAIL on darwin 8. PR 7886. 
llvm-svn: 111108
 2010-08-15 19:40:29 +00:00
Mikhail Glushenkov
de1e03e890 Update tests. 
llvm-svn: 111096
 2010-08-15 07:07:24 +00:00
Dan Gohman
afb3db46d2 LoopSimplify shouldn't split loop backedges that use indirectbr. PR7867. 
llvm-svn: 111061
 2010-08-14 00:43:09 +00:00
Dan Gohman
d04a608a73 Teach SimplifyCFG how to simplify indirectbr instructions. 
- Eliminate redundant successors.
 - Convert an indirectbr with one successor into a direct branch.

Also, generalize SimplifyCFG to be able to be run on a function entry block.
It knows quite a few simplifications which are applicable to the entry
block, and it only needs a few checks to avoid trouble with the entry block.

llvm-svn: 111060
 2010-08-14 00:29:42 +00:00
Dan Gohman
422c164d8d Add a lint check for an indirectbr destination which has not 
had its address taken.

llvm-svn: 111058
 2010-08-13 23:56:28 +00:00
Bob Wilson
92bf5a7425 Add a Thumb2 t2RSBrr instruction for disassembly only. 
This fixes another part of PR7792.

llvm-svn: 111057
 2010-08-13 23:24:25 +00:00
Bob Wilson
ca672ee828 Temporarily disable tail calls on ARM to work around some linker problems. 
llvm-svn: 111050
 2010-08-13 22:43:33 +00:00
Bob Wilson
0883c6aae3 Move the Thumb2 SSAT and USAT optional shift operator out of the 
instruction opcode.  This fixes part of PR7792.

llvm-svn: 111047
 2010-08-13 21:48:10 +00:00
Dale Johannesen
3f9c148d0e Revert 110491. While not wrong, it was based on a 
misanalysis and is undesirable.

llvm-svn: 111028
 2010-08-13 18:43:45 +00:00
Mikhail Glushenkov
003526ceac One more XFAIL. 
llvm-svn: 111010
 2010-08-13 07:03:56 +00:00
Mikhail Glushenkov
0728ed703a More XFAILs. 
llvm-svn: 111008
 2010-08-13 07:01:55 +00:00
Mikhail Glushenkov
104be4cd20 Add an XFAIL. 
llvm-svn: 111004
 2010-08-13 04:15:45 +00:00
Mikhail Glushenkov
74fa906ef0 Remove -fexceptions from llvmc tests. 
llvm-svn: 110999
 2010-08-13 02:29:35 +00:00
Mikhail Glushenkov
d4d9dbc382 llvmc: fix two tests, remove XFAILs. 
Tested on Linux and Darwin; please add platform-specific XFAILs/mail me a bug
report if this still fails.

llvm-svn: 110998
 2010-08-13 02:29:24 +00:00
Nate Begeman
e57074fc48 Reapply this transformation now that it is passing the external test which it previously failed. 
llvm-svn: 110987
 2010-08-13 00:17:53 +00:00
Chris Lattner
fd40059e71 fix PR7876: If ipsccp decides that a function's address is taken 
before it rewrites the code, we need to use that in the post-rewrite pass.

llvm-svn: 110962
 2010-08-12 22:25:23 +00:00
Johnny Chen
78345b1dfe Cleaned up the for-disassembly-only entries in the arm instruction table so that 
the memory barrier variants (other than 'SY' full system domain read and write)
are treated as one instruction with option operand.

llvm-svn: 110951
 2010-08-12 20:46:17 +00:00
Bruno Cardoso Lopes
7cb26cb8be - Teach SSEDomainFix to switch between different levels of AVX instructions. Here we guess that AVX will have domain issues, so just implement them for consistency and in the future we remove if it's unnecessary. 
- Make foldMemoryOperandImpl aware of 256-bit zero vectors folding and support the 128-bit counterparts of AVX too.
- Make sure MOV[AU]PS instructions are only selected when SSE1 is enabled, and duplicate the patterns to match AVX.
- Add a testcase for a simple 128-bit zero vector creation.

llvm-svn: 110946
 2010-08-12 20:20:53 +00:00
Bob Wilson
c6c469889b Add a test for llvm-gcc svn 110632. 
llvm-svn: 110935
 2010-08-12 17:31:41 +00:00
Eric Christopher
34acdf57df Temporarily revert 110737 and 110734, they were causing failures 
in an external testsuite.

llvm-svn: 110905
 2010-08-12 07:01:22 +00:00
Bruno Cardoso Lopes
bb491bd56c Begin to support some vector operations for AVX 256-bit intructions. The long 
term goal here is to be able to match enough of vector_shuffle and build_vector
so all avx intrinsics which aren't mapped to their own built-ins but to
shufflevector calls can be codegen'd. This is the first (baby) step, support
building zeroed vectors.

llvm-svn: 110897
 2010-08-12 02:06:36 +00:00
Johnny Chen
fef1367b50 The autogened decoder was confusing the ARM STRBT for ARM USAT, because the .td 
entry for ARM STRBT is actually a super-instruction for A8.6.199 STRBT A1 & A2.
Recover by looking for ARM:USAT encoding pattern before delegating to the auto-
gened decoder.

Added a "usat" test case to arm-tests.txt.

llvm-svn: 110894
 2010-08-12 01:40:54 +00:00
Daniel Dunbar
4f45de1b1e MC/X86/AsmParser: Give an explicit error message when we reject an instruction 
because it could have an ambiguous suffix.

llvm-svn: 110890
 2010-08-12 00:55:42 +00:00
Devang Patel
66fc7d88ae This is x86 only test. 
llvm-svn: 110887
 2010-08-12 00:17:38 +00:00
Johnny Chen
9a37d16281 Changed the format of DMBsy, DSBsy, and friends from Pseudo to MiscFrm. 
Added two test cases to arm-tests.txt.

llvm-svn: 110880
 2010-08-11 23:35:12 +00:00
Bob Wilson
3582107cf8 Move the ARM SSAT and USAT optional shift amount operand out of the 
instruction opcode.  This also fixes part of PR7792.

llvm-svn: 110875
 2010-08-11 23:10:46 +00:00
Bruno Cardoso Lopes
2051068483 Add testcases for all AVX 256-bit intrinsics added in the last couple days 
llvm-svn: 110854
 2010-08-11 21:12:09 +00:00
Bruno Cardoso Lopes
fa19084e79 Reapply r109881 using a more strict command line for llc. 
llvm-svn: 110833
 2010-08-11 17:39:23 +00:00
Jim Grosbach
401709255b fix silly typo 
llvm-svn: 110831
 2010-08-11 17:32:46 +00:00
Jim Grosbach
be1b6086b3 Add a target triple, as the runtime library invocation varies a bit by 
platform. It's apparently "bl __muldf3" on linux, for example. Since that's
not what we're checking here, it's more robust to just force a triple. We
just wwant to check that the inline FP instructions are only generated
on cpus that have them."

llvm-svn: 110830
 2010-08-11 17:31:12 +00:00
Evan Cheng
c25cd5a82e Fix test and re-enable it. 
llvm-svn: 110829
 2010-08-11 17:25:51 +00:00
Dan Gohman
afbb9c2f2e Temporarily disable some failing tests, until they can be 
properly investigated.

llvm-svn: 110825
 2010-08-11 16:36:07 +00:00
Jim Grosbach
1128a47289 cortex m4 has floating point support, but only single precision. 
llvm-svn: 110810
 2010-08-11 15:44:15 +00:00
Dan Gohman
7b88985ebd Temporarily disable some failing tests, until they can be 
properly investigated.

llvm-svn: 110808
 2010-08-11 15:09:00 +00:00
Bill Wendling
f10d5c00fc Consider this code snippet: 
float t1(int argc) {
  return (argc == 1123) ? 1.234f : 2.38213f;
}

We would generate truly awful code on ARM (those with a weak stomach should look
away):

_t1:
  movw   r1, #1123
  movs   r2, #1
  movs   r3, #0
  cmp    r0, r1
  mov.w  r0, #0
  it     eq
  moveq  r0, r2
  movs   r1, #4
  cmp    r0, #0
  it     ne
  movne  r3, r1
  adr    r0, #LCPI1_0
  ldr    r0, [r0, r3]
  bx     lr

The problem was that legalization was creating a cascade of SELECT_CC nodes, for
for the comparison of "argc == 1123" which was fed into a SELECT node for the ?:
statement which was itself converted to a SELECT_CC node. This is because the
ARM back-end doesn't have custom lowering for SELECT nodes, so it used the
default "Expand".

I added a fairly simple "LowerSELECT" to the ARM back-end. It takes care of this
testcase, but can obviously be expanded to include more cases.

Now we generate this, which looks optimal to me:

_t1:
  movw   r1, #1123
  movs   r2, #0
  cmp    r0, r1
  adr    r0, #LCPI0_0
  it     eq
  moveq  r2, #4
  ldr    r0, [r0, r2]
  bx     lr
  .align  2
LCPI0_0:
  .long   1075344593  @ float 2.382130e+00
  .long   1067316150  @ float 1.234000e+00

llvm-svn: 110799
 2010-08-11 08:43:16 +00:00
Evan Cheng
f8604b772e Report error if codegen tries to instantiate a ARM target when the cpu does support it. e.g. cortex-m* processors. 
llvm-svn: 110798
 2010-08-11 07:17:46 +00:00
Evan Cheng
273160895e Add ARM Archv6M and let it implies FeatureDB (having dmb, etc.) 
llvm-svn: 110795
 2010-08-11 06:51:54 +00:00
Daniel Dunbar
bc7c0a60da MC/ARM: Add basic support for handling predication by parsing it out of the mnemonic into a separate operand form. 
llvm-svn: 110794
 2010-08-11 06:37:20 +00:00