14917 Commits

Author SHA1 Message Date
Bruno Cardoso Lopes
632295a03c Support x86 "eiz" and "riz" pseudo index registers in the assembler.
llvm-svn: 109295
2010-07-24 00:06:39 +00:00
Jim Grosbach
4b7545413d Use the appropriate register class for an i32 when adding ARM::LR to the
function live in set. This will give us tGPR for Thumb1 and GPR otherwise,
so the copy will be spillable. rdar://8224931

llvm-svn: 109293
2010-07-23 23:50:35 +00:00
Dale Johannesen
50d2bc2942 Revert 109076. It is wrong and was causing regressions. Add some
comments explaining why it was wrong.  8225024.

Fix the real problem in 8213383: the code that splits very large
blocks when no other place to put constants can be found was not
considering the case that the block contained a Thumb tablejump.

llvm-svn: 109282
2010-07-23 22:50:23 +00:00
Evan Cheng
f215e55d5f - Allow target to specify when is register pressure "too high". In most cases,
it's too late to start backing off aggressive latency scheduling when most
  of the registers are in use so the threshold should be a bit tighter.
- Correctly handle live out's and extract_subreg etc.
- Enable register pressure aware scheduling by default for hybrid scheduler.
  For ARM, this is almost always a win on # of instructions. It's runtime
  neutral for most of the tests. But for some kernels with high register
  pressure it can be a huge win. e.g. 464.h264ref reduced number of spills by
  54 and sped up by 20%.

llvm-svn: 109279
2010-07-23 22:39:59 +00:00
Bruno Cardoso Lopes
06fcdd6563 Remove trailing whitespace
llvm-svn: 109276
2010-07-23 22:15:26 +00:00
Bruno Cardoso Lopes
a80b57e5fc Add AVX version of CLMUL instructions
llvm-svn: 109248
2010-07-23 18:41:12 +00:00
Gabor Greif
30f8e2112c fix constness warnings
llvm-svn: 109224
2010-07-23 13:28:47 +00:00
Gabor Greif
a04ffe0391 do not (implicitly) dereference iterator many times, cache it instead
llvm-svn: 109222
2010-07-23 10:23:01 +00:00
Bruno Cardoso Lopes
b5374c4b69 Declare CLMUL as a subtarget feature
llvm-svn: 109207
2010-07-23 01:22:45 +00:00
Bruno Cardoso Lopes
b034ffa291 Add x86 CLMUL (Carry-less multiplication) cpu feature
llvm-svn: 109206
2010-07-23 01:17:51 +00:00
Bruno Cardoso Lopes
b9182e3051 Add complete assembler support for FMA3 instructions, with descriptions and encodings taken from the AVX manual
llvm-svn: 109204
2010-07-23 00:54:35 +00:00
Dale Johannesen
1ee436f417 The only supported calling convention for X86-64 uses
SSE, so we can't return floating point values if this
is disabled.  Detect this error for clang.

With SSE1 only, f64 is a problem; it can be done, but
neither llvm-gcc nor clang has ever generated correct
code for it.  Since nobody noticed this I think it's
OK to treat it as an error for now.

This also handles SSE-sized vectors of floating point.
8207686, 8204109.

llvm-svn: 109201
2010-07-23 00:30:35 +00:00
Bruno Cardoso Lopes
93fd8bdf6a Fix some AVX instructions which didnt had HasAVX prefix. And also a problem with PINSRW, which was totally wrong because of a typo I introduced previously
llvm-svn: 109198
2010-07-23 00:14:54 +00:00
Chris Lattner
a1dcdf0bd4 eliminate the TargetInstrInfo::GetInstSizeInBytes hook.
ARM/PPC/MSP430-specific code (which are the only targets that
implement the hook) can directly reference their target-specific
instrinfo classes.

llvm-svn: 109171
2010-07-22 21:27:00 +00:00
Bruno Cardoso Lopes
7722724eee Add remaining AVX instructions (most of them dealing with GR64 destinations. This complete the assembler support for the general AVX ISA. But we still miss instructions from FMA3 and CLMUL specific feature flags, which are now the next step
llvm-svn: 109168
2010-07-22 21:18:49 +00:00
Chris Lattner
65ad913bec remove the JIT "NeedsExactSize" feature and supporting logic.
llvm-svn: 109167
2010-07-22 21:17:55 +00:00
Chris Lattner
9c30949ae1 switch a private implementation of GetFunctionSizeInBytes.
This is probably not the best way to implement "Force LR to 
be spilled if the Thumb function size is > 2048." do this, 
it should use the branch shortening infrastructure, but I'm
just preserving functionality here.

llvm-svn: 109165
2010-07-22 21:14:33 +00:00
Chris Lattner
7704d56b21 X86MCInstLower now depends on AsmPrinter being around.
llvm-svn: 109154
2010-07-22 21:10:04 +00:00
Chris Lattner
367aa754b1 instead of migrating it to the MC instruction encoder, just
rip out the implementation of X86InstrInfo::GetInstSizeInBytes.
The code being ripped out just implemented a copy and hacked up
version of the (old) instruction encoder, and is buggy and 
terrible in other ways.  Since "GetInstSizeInBytes" is really 
only there to support the JIT's "NeedsExactSize" hook (which
noone is using), just rip out the code.  I will rip out the
NeedsExactSize hook next.

This resolves rdar://7617809 - switch X86InstrInfo::GetInstSizeInBytes to use X86MCCodeEmitter

llvm-svn: 109149
2010-07-22 21:05:13 +00:00
Xerxes Ranby
c7a04bcaa5 ARMv4 JIT forgets to set the lr register when making a indirect function call. Fixes PR7608
llvm-svn: 109125
2010-07-22 17:28:34 +00:00
Gabor Greif
a7509fca78 undo 80 column trespassing I caused
llvm-svn: 109092
2010-07-22 10:37:47 +00:00
Chandler Carruth
e10953d673 Mark an assert-only variable as used.
llvm-svn: 109091
2010-07-22 08:02:25 +00:00
Chandler Carruth
4810e179e9 Fix the generated file name for CMake.
llvm-svn: 109090
2010-07-22 08:00:52 +00:00
Chandler Carruth
66edf31b8e Attempt to fix linking issues with CMake. Please review other CMake users,
especially on other platforms. Is there a better way to fix this.

llvm-svn: 109084
2010-07-22 06:27:45 +00:00
Owen Anderson
01e73ac583 Update CMake files.
llvm-svn: 109081
2010-07-22 06:00:01 +00:00
Eric Christopher
4924d5fb93 Custom lower the memory barrier instructions and add support
for lowering without sse2.  Add a couple of new testcases.

Fixes a few libgomp tests and latent bugs.  Remove a few todos.

llvm-svn: 109078
2010-07-22 02:48:34 +00:00
Evan Cheng
32f6aba7d8 Fix constant island pass's handling of tBR_JTr. The offset of the instruction does not have to be 4-byte aligned. Rather, it's the offset + 2 that must be aligned since the instruction expands into:
mov     pc, r1
        .align  2
LJTI0_0_0:
        .long    LBB0_14

This fixes rdar://8213383. No test case since it's not possible to come up with a suitable small one.

llvm-svn: 109076
2010-07-22 02:09:47 +00:00
Eric Christopher
5901214b6a 80-columns.
llvm-svn: 109070
2010-07-22 00:26:08 +00:00
Nate Begeman
c50bef0df7 Make fast isel win64-aware w.r.t. call-clobbered regs
llvm-svn: 109069
2010-07-22 00:09:39 +00:00
Evan Cheng
5aa6a25102 More register pressure aware scheduling work.
llvm-svn: 109064
2010-07-21 23:53:58 +00:00
Bruno Cardoso Lopes
5920e38cd2 Add more 256-bit forms for a bunch of regular AVX instructions
Add 64-bit (GR64) versions of some instructions (which are not
described in their SSE forms, but are described in AVX)

llvm-svn: 109063
2010-07-21 23:53:50 +00:00
Rafael Espindola
c8342b43c4 Fixes win64. It was broken by a previous patch where I missed the !isWin64
and then forced every register to be a vr128 on win64.

llvm-svn: 109060
2010-07-21 23:19:57 +00:00
Jim Grosbach
489d758ea8 For ARM/Darwin, add a dwarf entry indicating whether a function is arm or thumb
rdar://8202967

llvm-svn: 109057
2010-07-21 23:03:52 +00:00
Chris Lattner
418c190d93 add some rough support for making mcinst lowering work without an
asmprinter or mangler around.  This is option #B for killing off 
X86InstrInfo::GetInstSizeInBytes.  Option #A (killing 
"needsexactsize") was sent for consideration to llvmdev.

llvm-svn: 109056
2010-07-21 23:03:35 +00:00
Eric Christopher
3d118d5e8a Baby steps towards ARM fast-isel.
llvm-svn: 109047
2010-07-21 22:26:11 +00:00
Owen Anderson
f8addbb0a1 Fix batch of converting RegisterPass<> to INTIALIZE_PASS().
llvm-svn: 109045
2010-07-21 22:09:45 +00:00
Bruno Cardoso Lopes
eea3b7ed83 Add missing AVX convert instructions. Those instructions are not described in their SSE forms (although they exist), but add the AVX forms anyway, so the assembler can benefit from it
llvm-svn: 109039
2010-07-21 21:37:59 +00:00
Nate Begeman
e7ca21ab3b Fix a couple issues with Win64 ABI
1) all registers were spilled as xmm, regardless of actual size
2) win64 abi doesn't do the varargs-size-in-%al thing

Still to look into:

xmm6-15 are marked as clobbered by call instructions on win64 even though they aren't.

llvm-svn: 109035
2010-07-21 20:49:52 +00:00
Bruno Cardoso Lopes
1284fdc932 Avoid AVX instructions to be selected instead of its SSE form
llvm-svn: 109032
2010-07-21 20:38:42 +00:00
Rafael Espindola
9aab8413b8 Fix calling convention on ARM if vfp2+ is enabled.
llvm-svn: 109009
2010-07-21 11:38:30 +00:00
Eric Christopher
959481ec87 Pulling out previous patch, must've run the tests in
the wrong directory.

llvm-svn: 109005
2010-07-21 09:23:56 +00:00
Eric Christopher
5c12ad2a4b Lower MEMBARRIER on x86 and support processors without SSE2.
Fixes a pile of libgomp failures in the llvm-gcc testsuite due
to the libcall not existing.

llvm-svn: 109004
2010-07-21 09:05:23 +00:00
Bruno Cardoso Lopes
d13d8c2562 Add AVX only vzeroall and vzeroupper instructions
llvm-svn: 109002
2010-07-21 08:56:24 +00:00
Evan Cheng
df725c25dd Teach bottom up pre-ra scheduler to track register pressure. Work in progress.
llvm-svn: 108991
2010-07-21 06:09:07 +00:00
Bruno Cardoso Lopes
c4d93a5a34 Add new AVX vpermilps, vpermilpd and vperm2f128 instructions
llvm-svn: 108984
2010-07-21 03:07:42 +00:00
Bruno Cardoso Lopes
a7efb29695 Add new AVX vmaskmov instructions, and also fix the VEX encoding bits to support it
llvm-svn: 108983
2010-07-21 02:46:58 +00:00
Bruno Cardoso Lopes
e0dce1c741 Add new AVX vextractf128 instructions
llvm-svn: 108964
2010-07-20 23:19:02 +00:00
Chris Lattner
fa1479a813 make asmprinter optional, even though passing in null will cause things to explode right now.
llvm-svn: 108955
2010-07-20 22:45:33 +00:00
Chris Lattner
535d070a96 continue pushing dependencies around.
llvm-svn: 108952
2010-07-20 22:35:40 +00:00
Chris Lattner
607e343ee1 reduce X86MCInstLower dependencies on asmprinter.
llvm-svn: 108950
2010-07-20 22:30:53 +00:00