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94988510e6
Adds ARMBankConflictHazardRecognizer. This hazard recognizer looks for a few situations where the same base pointer is used and then checks whether the offsets lead to a bank conflict. Two parameters are also added to permit overriding of the target assumptions: arm-data-bank-mask=<int> - Mask of bits which are to be checked for conflicts. If all these bits are equal in the offsets, there is a conflict. arm-assume-itcm-bankconflict=<bool> - Assume that there will be bank conflicts on any loads to a constant pool. This hazard recognizer is enabled for Cortex-M7, where the Technical Reference Manual states that there are two DTCM banks banked using bit 2 and one ITCM bank. Differential Revision: https://reviews.llvm.org/D93054
70 lines
2.0 KiB
C++
70 lines
2.0 KiB
C++
//===-- ARMHazardRecognizer.h - ARM Hazard Recognizers ----------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines hazard recognizers for scheduling ARM functions.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_ARM_ARMHAZARDRECOGNIZER_H
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#define LLVM_LIB_TARGET_ARM_ARMHAZARDRECOGNIZER_H
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#include "ARMBaseInstrInfo.h"
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#include "llvm/ADT/BitmaskEnum.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
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#include "llvm/Support/DataTypes.h"
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#include <array>
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#include <initializer_list>
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namespace llvm {
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class DataLayout;
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class MachineFunction;
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class MachineInstr;
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class ScheduleDAG;
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// Hazards related to FP MLx instructions
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class ARMHazardRecognizerFPMLx : public ScheduleHazardRecognizer {
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MachineInstr *LastMI = nullptr;
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unsigned FpMLxStalls = 0;
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public:
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ARMHazardRecognizerFPMLx() : ScheduleHazardRecognizer() { MaxLookAhead = 1; }
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HazardType getHazardType(SUnit *SU, int Stalls) override;
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void Reset() override;
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void EmitInstruction(SUnit *SU) override;
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void AdvanceCycle() override;
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void RecedeCycle() override;
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};
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// Hazards related to bank conflicts
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class ARMBankConflictHazardRecognizer : public ScheduleHazardRecognizer {
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SmallVector<MachineInstr *, 8> Accesses;
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const MachineFunction &MF;
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const DataLayout &DL;
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int64_t DataMask;
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bool AssumeITCMBankConflict;
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public:
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ARMBankConflictHazardRecognizer(const ScheduleDAG *DAG, int64_t DDM,
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bool ABC);
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HazardType getHazardType(SUnit *SU, int Stalls) override;
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void Reset() override;
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void EmitInstruction(SUnit *SU) override;
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void AdvanceCycle() override;
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void RecedeCycle() override;
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private:
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inline HazardType CheckOffsets(unsigned O0, unsigned O1);
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};
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} // end namespace llvm
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#endif
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