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7d816e3012
On targets like Arm some relaxations may only be performed when certain architectural features are available. As functions can be compiled with differing levels of architectural support we must make a judgement on whether we can relax based on the MCSubtargetInfo for the function. This change passes through the MCSubtargetInfo for the function to fixupNeedsRelaxation so that the decision on whether to relax can be made per function. In this patch, only the ARM backend makes use of this information. We must also pass the MCSubtargetInfo to applyFixup because some fixups skip error checking on the assumption that relaxation has occurred, to prevent code-generation errors applyFixup must see the same MCSubtargetInfo as fixupNeedsRelaxation. Differential Revision: https://reviews.llvm.org/D44928 llvm-svn: 334078
34 lines
910 B
ArmAsm
34 lines
910 B
ArmAsm
# RUN: llvm-mc -filetype=obj -triple armv7-linux-gnueabi %s -o - \
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# RUN: | llvm-objdump -no-show-raw-insn -triple armv7 -disassemble - | FileCheck %s
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# We can switch subtargets with .arch outside of a bundle
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.syntax unified
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.text
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.bundle_align_mode 4
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.arch armv4t
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bx lr
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.bundle_lock
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and r1, r1, r1
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and r1, r1, r1
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.bundle_unlock
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bx lr
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# We can switch subtargets at the start of a bundle
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bx lr
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.bundle_lock align_to_end
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.arch armv7a
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movt r0, #0xffff
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movw r0, #0xffff
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.bundle_unlock
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bx lr
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# CHECK: 0: bx lr
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# CHECK-NEXT: 4: and r1, r1, r1
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# CHECK-NEXT: 8: and r1, r1, r1
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# CHECK-NEXT: c: bx lr
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# CHECK-NEXT: 10: bx lr
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# CHECK-NEXT: 14: nop
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# CHECK-NEXT: 18: movt r0, #65535
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# CHECK-NEXT: 1c: movw r0, #65535
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# CHECK-NEXT: 20: bx lr
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