llvm-mirror/test/MC/RISCV
Alex Bradbury 00d29ca310 [RISCV] implement li pseudo instruction
The implementation follows the MIPS backend and expands the
pseudo instruction directly during asm parsing. As the result, only
real MC instructions are emitted to the MCStreamer. Additionally,
PseudoLI instructions are emitted during codegen. The actual
expansion to real instructions is performed during MI to MC lowering
and is similar to the expansion performed by the GNU Assembler.

Differential Revision: https://reviews.llvm.org/D41949
Patch by Mario Werner.

llvm-svn: 330224
2018-04-17 21:56:40 +00:00
..
cnop.s [RISCV] Tablegen-driven Instruction Compression. 2018-04-06 21:07:05 +00:00
compress-cjal.s [RISCV] Tablegen-driven Instruction Compression. 2018-04-06 21:07:05 +00:00
compress-rv32d.s [RISCV] Tablegen-driven Instruction Compression. 2018-04-06 21:07:05 +00:00
compress-rv32f.s [RISCV] Tablegen-driven Instruction Compression. 2018-04-06 21:07:05 +00:00
compress-rv32i.s [RISCV] Add c.mv rs1, rs2 pattern for addi rs1, rs2, 0 2018-04-12 19:22:40 +00:00
compress-rv64i.s [RISCV] Tablegen-driven Instruction Compression. 2018-04-06 21:07:05 +00:00
compressed-relocations.s [RISCV] Tablegen-driven Instruction Compression. 2018-04-06 21:07:05 +00:00
csr-aliases.s [RISCV] Pass MCSubtargetInfo to print methods. 2018-01-12 02:27:00 +00:00
elf-flags.s [RISCV] Encode RISCV specific ELF e_flags to RISCV Binary by RISCVTargetStreamer 2018-01-26 07:53:07 +00:00
elf-header.s [RISCV] Bugfix createRISCVELFObjectWriter 2017-10-18 16:11:31 +00:00
fixups-compressed.s [RISCV] Tablegen-driven Instruction Compression. 2018-04-06 21:07:05 +00:00
fixups-diagnostics.s [RISCV] Add common fixups and relocations 2017-09-28 08:26:24 +00:00
fixups.s [RISCV] Enable emission of alias instructions by default 2017-12-15 09:47:01 +00:00
hilo-constaddr.s [RISCV] Add common fixups and relocations 2017-09-28 08:26:24 +00:00
lit.local.cfg
priv-invalid.s [RISCV] Define sfence.vma InstAliases to match the GNU RISC-V tools 2017-12-13 12:46:55 +00:00
priv-valid.s [RISCV] Enable emission of alias instructions by default 2017-12-15 09:47:01 +00:00
relocations.s [RISCV] Tablegen-driven Instruction Compression. 2018-04-06 21:07:05 +00:00
rv32-relaxation.s [RISCV] Tablegen-driven Instruction Compression. 2018-04-06 21:07:05 +00:00
rv32a-invalid.s [RISCV] MC layer support for the standard RV64A instruction set extension 2017-12-07 10:59:12 +00:00
rv32a-valid.s [RISCV] Enable emission of alias instructions by default 2017-12-15 09:47:01 +00:00
rv32c-invalid.s [RISCV] Implement c.lui immediate operand constraint 2018-02-22 15:02:28 +00:00
rv32c-only-valid.s [RISCV] Update MC compression tests 2018-04-06 18:27:45 +00:00
rv32c-valid.s [RISCV] Implement c.lui immediate operand constraint 2018-02-22 15:02:28 +00:00
rv32d-invalid.s [RISCV] MC layer support for the standard RV32D instruction set extension 2017-12-07 10:46:23 +00:00
rv32d-valid.s [RISCV] Enable emission of alias instructions by default 2017-12-15 09:47:01 +00:00
rv32dc-invalid.s [RISCV] MC layer support for the remaining RVC instructions 2017-12-13 09:32:55 +00:00
rv32dc-valid.s [RISCV] Add ELFObjectFileBase::getRISCVFeatures let llvm-objdump could get RISCV target feature 2018-02-02 06:01:02 +00:00
rv32f-invalid.s [RISCV] MC layer support for the standard RV64F instruction set extension 2017-12-07 11:02:55 +00:00
rv32f-valid.s [RISCV] Enable emission of alias instructions by default 2017-12-15 09:47:01 +00:00
rv32fc-invalid.s [RISCV] MC layer support for the remaining RVC instructions 2017-12-13 09:32:55 +00:00
rv32fc-valid.s [RISCV] Add ELFObjectFileBase::getRISCVFeatures let llvm-objdump could get RISCV target feature 2018-02-02 06:01:02 +00:00
rv32i-aliases-invalid.s [RISCV] implement li pseudo instruction 2018-04-17 21:56:40 +00:00
rv32i-aliases-valid.s [RISCV] implement li pseudo instruction 2018-04-17 21:56:40 +00:00
rv32i-invalid.s [RISCV] Add support for %pcrel_lo. 2018-02-06 00:55:23 +00:00
rv32i-valid.s [RISCV] Enable emission of alias instructions by default 2017-12-15 09:47:01 +00:00
rv32m-invalid.s [RISCV] MC layer support for the standard RV64M instruction set extension 2017-12-07 10:56:07 +00:00
rv32m-valid.s [RISCV] Enable emission of alias instructions by default 2017-12-15 09:47:01 +00:00
rv64-relaxation.s [RISCV] Tablegen-driven Instruction Compression. 2018-04-06 21:07:05 +00:00
rv64a-invalid.s [RISCV] MC layer support for the standard RV64A instruction set extension 2017-12-07 10:59:12 +00:00
rv64a-valid.s [RISCV] Enable emission of alias instructions by default 2017-12-15 09:47:01 +00:00
rv64c-invalid.s [RISCV] Change shift amount operand of RVC shift instructions to uimmlog2xlennonzero 2017-12-15 10:20:51 +00:00
rv64c-valid.s [RISCV] Add ELFObjectFileBase::getRISCVFeatures let llvm-objdump could get RISCV target feature 2018-02-02 06:01:02 +00:00
rv64d-aliases-valid.s [RISCV] Enable emission of alias instructions by default 2017-12-15 09:47:01 +00:00
rv64d-invalid.s [RISCV] Add missed tests for RV64D MC layer support 2017-12-07 11:05:38 +00:00
rv64d-valid.s [RISCV] Enable emission of alias instructions by default 2017-12-15 09:47:01 +00:00
rv64dc-valid.s [RISCV] Add ELFObjectFileBase::getRISCVFeatures let llvm-objdump could get RISCV target feature 2018-02-02 06:01:02 +00:00
rv64f-aliases-valid.s [RISCV] Enable emission of alias instructions by default 2017-12-15 09:47:01 +00:00
rv64f-invalid.s [RISCV] MC layer support for the standard RV64F instruction set extension 2017-12-07 11:02:55 +00:00
rv64f-valid.s [RISCV] Enable emission of alias instructions by default 2017-12-15 09:47:01 +00:00
rv64i-aliases-invalid.s [RISCV] implement li pseudo instruction 2018-04-17 21:56:40 +00:00
rv64i-aliases-valid.s [RISCV] implement li pseudo instruction 2018-04-17 21:56:40 +00:00
rv64i-invalid.s [RISCV] MC layer support for the standard RV64I instructions 2017-12-07 10:53:48 +00:00
rv64i-valid.s [RISCV] Enable emission of alias instructions by default 2017-12-15 09:47:01 +00:00
rv64m-valid.s [RISCV] Enable emission of alias instructions by default 2017-12-15 09:47:01 +00:00
rvd-aliases-valid.s [RISCV] Enable emission of alias instructions by default 2017-12-15 09:47:01 +00:00
rvf-aliases-valid.s [RISCV] Enable emission of alias instructions by default 2017-12-15 09:47:01 +00:00
rvi-aliases-valid.s [RISCV] implement li pseudo instruction 2018-04-17 21:56:40 +00:00