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012d53ce0b
Summary: The AsmParser Lexer regards these as a seperate token. Here we expand the instruction name with them if they are adjacent (no whitespace). Tested: the basic-assembly.s test case has one case with a / in it. The currently are also instructions with : in them, which we intend to rename rather than fix them here. Reviewers: tlively, dschuff Subscribers: sbc100, jgravelle-google, aheejin, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52442 llvm-svn: 343501
409 lines
14 KiB
C++
409 lines
14 KiB
C++
//==- WebAssemblyAsmParser.cpp - Assembler for WebAssembly -*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file is part of the WebAssembly Assembler.
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///
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/// It contains code to translate a parsed .s file into MCInsts.
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///
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
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#include "MCTargetDesc/WebAssemblyTargetStreamer.h"
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#include "WebAssembly.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
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#include "llvm/MC/MCParser/MCTargetAsmParser.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Support/Endian.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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#define DEBUG_TYPE "wasm-asm-parser"
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namespace {
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/// WebAssemblyOperand - Instances of this class represent the operands in a
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/// parsed WASM machine instruction.
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struct WebAssemblyOperand : public MCParsedAsmOperand {
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enum KindTy { Token, Integer, Float, Symbol } Kind;
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SMLoc StartLoc, EndLoc;
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struct TokOp {
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StringRef Tok;
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};
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struct IntOp {
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int64_t Val;
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};
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struct FltOp {
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double Val;
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};
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struct SymOp {
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const MCExpr *Exp;
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};
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union {
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struct TokOp Tok;
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struct IntOp Int;
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struct FltOp Flt;
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struct SymOp Sym;
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};
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WebAssemblyOperand(KindTy K, SMLoc Start, SMLoc End, TokOp T)
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: Kind(K), StartLoc(Start), EndLoc(End), Tok(T) {}
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WebAssemblyOperand(KindTy K, SMLoc Start, SMLoc End, IntOp I)
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: Kind(K), StartLoc(Start), EndLoc(End), Int(I) {}
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WebAssemblyOperand(KindTy K, SMLoc Start, SMLoc End, FltOp F)
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: Kind(K), StartLoc(Start), EndLoc(End), Flt(F) {}
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WebAssemblyOperand(KindTy K, SMLoc Start, SMLoc End, SymOp S)
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: Kind(K), StartLoc(Start), EndLoc(End), Sym(S) {}
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bool isToken() const override { return Kind == Token; }
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bool isImm() const override {
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return Kind == Integer || Kind == Float || Kind == Symbol;
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}
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bool isMem() const override { return false; }
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bool isReg() const override { return false; }
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unsigned getReg() const override {
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llvm_unreachable("Assembly inspects a register operand");
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return 0;
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}
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StringRef getToken() const {
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assert(isToken());
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return Tok.Tok;
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}
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SMLoc getStartLoc() const override { return StartLoc; }
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SMLoc getEndLoc() const override { return EndLoc; }
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void addRegOperands(MCInst &, unsigned) const {
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// Required by the assembly matcher.
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llvm_unreachable("Assembly matcher creates register operands");
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}
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void addImmOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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if (Kind == Integer)
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Inst.addOperand(MCOperand::createImm(Int.Val));
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else if (Kind == Float)
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Inst.addOperand(MCOperand::createFPImm(Flt.Val));
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else if (Kind == Symbol)
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Inst.addOperand(MCOperand::createExpr(Sym.Exp));
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else
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llvm_unreachable("Should be immediate or symbol!");
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}
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void print(raw_ostream &OS) const override {
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switch (Kind) {
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case Token:
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OS << "Tok:" << Tok.Tok;
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break;
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case Integer:
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OS << "Int:" << Int.Val;
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break;
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case Float:
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OS << "Flt:" << Flt.Val;
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break;
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case Symbol:
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OS << "Sym:" << Sym.Exp;
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break;
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}
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}
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};
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class WebAssemblyAsmParser final : public MCTargetAsmParser {
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MCAsmParser &Parser;
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MCAsmLexer &Lexer;
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MCSymbol *LastLabel;
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public:
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WebAssemblyAsmParser(const MCSubtargetInfo &sti, MCAsmParser &Parser,
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const MCInstrInfo &mii, const MCTargetOptions &Options)
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: MCTargetAsmParser(Options, sti, mii), Parser(Parser),
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Lexer(Parser.getLexer()), LastLabel(nullptr) {
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setAvailableFeatures(ComputeAvailableFeatures(sti.getFeatureBits()));
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}
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#define GET_ASSEMBLER_HEADER
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#include "WebAssemblyGenAsmMatcher.inc"
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// TODO: This is required to be implemented, but appears unused.
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bool ParseRegister(unsigned & /*RegNo*/, SMLoc & /*StartLoc*/,
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SMLoc & /*EndLoc*/) override {
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llvm_unreachable("ParseRegister is not implemented.");
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}
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bool Error(const StringRef &msg, const AsmToken &tok) {
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return Parser.Error(tok.getLoc(), msg + tok.getString());
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}
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bool IsNext(AsmToken::TokenKind Kind) {
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auto ok = Lexer.is(Kind);
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if (ok)
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Parser.Lex();
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return ok;
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}
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bool Expect(AsmToken::TokenKind Kind, const char *KindName) {
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if (!IsNext(Kind))
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return Error(std::string("Expected ") + KindName + ", instead got: ",
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Lexer.getTok());
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return false;
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}
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MVT::SimpleValueType ParseRegType(const StringRef &RegType) {
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// Derive type from .param .local decls, or the instruction itself.
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return StringSwitch<MVT::SimpleValueType>(RegType)
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.Case("i32", MVT::i32)
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.Case("i64", MVT::i64)
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.Case("f32", MVT::f32)
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.Case("f64", MVT::f64)
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.Case("i8x16", MVT::v16i8)
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.Case("i16x8", MVT::v8i16)
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.Case("i32x4", MVT::v4i32)
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.Case("i64x2", MVT::v2i64)
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.Case("f32x4", MVT::v4f32)
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.Case("f64x2", MVT::v2f64)
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// arbitrarily chosen vector type to associate with "v128"
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// FIXME: should these be EVTs to avoid this arbitrary hack? Do we want
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// to accept more specific SIMD register types?
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.Case("v128", MVT::v16i8)
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.Default(MVT::INVALID_SIMPLE_VALUE_TYPE);
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}
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void ParseSingleInteger(bool IsNegative, OperandVector &Operands) {
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auto &Int = Lexer.getTok();
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int64_t Val = Int.getIntVal();
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if (IsNegative)
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Val = -Val;
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Operands.push_back(make_unique<WebAssemblyOperand>(
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WebAssemblyOperand::Integer, Int.getLoc(), Int.getEndLoc(),
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WebAssemblyOperand::IntOp{Val}));
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Parser.Lex();
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}
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bool ParseOperandStartingWithInteger(bool IsNegative, OperandVector &Operands,
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StringRef InstName) {
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ParseSingleInteger(IsNegative, Operands);
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// FIXME: there is probably a cleaner way to do this.
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auto IsLoadStore = InstName.startswith("load") ||
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InstName.startswith("store") ||
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InstName.startswith("atomic_load") ||
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InstName.startswith("atomic_store");
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if (IsLoadStore) {
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// Parse load/store operands of the form: offset align
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auto &Offset = Lexer.getTok();
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if (Offset.is(AsmToken::Integer)) {
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ParseSingleInteger(false, Operands);
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} else {
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// Alignment not specified.
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// FIXME: correctly derive a default from the instruction.
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// We can't just call WebAssembly::GetDefaultP2Align since we don't have
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// an opcode until after the assembly matcher.
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Operands.push_back(make_unique<WebAssemblyOperand>(
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WebAssemblyOperand::Integer, Offset.getLoc(), Offset.getEndLoc(),
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WebAssemblyOperand::IntOp{0}));
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}
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}
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return false;
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}
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bool ParseInstruction(ParseInstructionInfo & /*Info*/, StringRef Name,
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SMLoc NameLoc, OperandVector &Operands) override {
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// Note: Name does NOT point into the sourcecode, but to a local, so
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// use NameLoc instead.
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Name = StringRef(NameLoc.getPointer(), Name.size());
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// WebAssembly has instructions with / in them, which AsmLexer parses
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// as seperate tokens, so if we find such tokens immediately adjacent (no
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// whitespace), expand the name to include them:
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for (;;) {
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auto &Sep = Lexer.getTok();
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if (Sep.getLoc().getPointer() != Name.end() ||
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Sep.getKind() != AsmToken::Slash) break;
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// Extend name with /
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Name = StringRef(Name.begin(), Name.size() + Sep.getString().size());
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Parser.Lex();
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// We must now find another identifier, or error.
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auto &Id = Lexer.getTok();
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if (Id.getKind() != AsmToken::Identifier ||
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Id.getLoc().getPointer() != Name.end())
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return Error("Incomplete instruction name: ", Id);
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Name = StringRef(Name.begin(), Name.size() + Id.getString().size());
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Parser.Lex();
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}
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// Now construct the name as first operand.
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Operands.push_back(make_unique<WebAssemblyOperand>(
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WebAssemblyOperand::Token, NameLoc, SMLoc::getFromPointer(Name.end()),
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WebAssemblyOperand::TokOp{Name}));
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auto NamePair = Name.split('.');
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// If no '.', there is no type prefix.
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auto BaseName = NamePair.second.empty() ? NamePair.first : NamePair.second;
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while (Lexer.isNot(AsmToken::EndOfStatement)) {
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auto &Tok = Lexer.getTok();
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switch (Tok.getKind()) {
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case AsmToken::Identifier: {
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auto &Id = Lexer.getTok();
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const MCExpr *Val;
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SMLoc End;
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if (Parser.parsePrimaryExpr(Val, End))
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return Error("Cannot parse symbol: ", Lexer.getTok());
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Operands.push_back(make_unique<WebAssemblyOperand>(
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WebAssemblyOperand::Symbol, Id.getLoc(), Id.getEndLoc(),
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WebAssemblyOperand::SymOp{Val}));
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break;
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}
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case AsmToken::Minus:
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Parser.Lex();
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if (Lexer.isNot(AsmToken::Integer))
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return Error("Expected integer instead got: ", Lexer.getTok());
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if (ParseOperandStartingWithInteger(true, Operands, BaseName))
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return true;
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break;
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case AsmToken::Integer:
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if (ParseOperandStartingWithInteger(false, Operands, BaseName))
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return true;
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break;
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case AsmToken::Real: {
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double Val;
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if (Tok.getString().getAsDouble(Val, false))
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return Error("Cannot parse real: ", Tok);
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Operands.push_back(make_unique<WebAssemblyOperand>(
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WebAssemblyOperand::Float, Tok.getLoc(), Tok.getEndLoc(),
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WebAssemblyOperand::FltOp{Val}));
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Parser.Lex();
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break;
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}
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default:
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return Error("Unexpected token in operand: ", Tok);
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}
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if (Lexer.isNot(AsmToken::EndOfStatement)) {
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if (Expect(AsmToken::Comma, ","))
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return true;
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}
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}
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Parser.Lex();
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// Block instructions require a signature index, but these are missing in
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// assembly, so we add a dummy one explicitly (since we have no control
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// over signature tables here, we assume these will be regenerated when
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// the wasm module is generated).
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if (BaseName == "block" || BaseName == "loop") {
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Operands.push_back(make_unique<WebAssemblyOperand>(
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WebAssemblyOperand::Integer, NameLoc, NameLoc,
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WebAssemblyOperand::IntOp{-1}));
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}
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return false;
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}
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void onLabelParsed(MCSymbol *Symbol) override { LastLabel = Symbol; }
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bool ParseDirective(AsmToken DirectiveID) override {
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assert(DirectiveID.getKind() == AsmToken::Identifier);
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auto &Out = getStreamer();
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auto &TOut =
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reinterpret_cast<WebAssemblyTargetStreamer &>(*Out.getTargetStreamer());
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// TODO: we're just parsing the subset of directives we're interested in,
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// and ignoring ones we don't recognise. We should ideally verify
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// all directives here.
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if (DirectiveID.getString() == ".type") {
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// This could be the start of a function, check if followed by
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// "label,@function"
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if (!(IsNext(AsmToken::Identifier) && IsNext(AsmToken::Comma) &&
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IsNext(AsmToken::At) && Lexer.is(AsmToken::Identifier)))
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return Error("Expected label,@type declaration, got: ", Lexer.getTok());
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Parser.Lex();
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// Out.EmitSymbolAttribute(??, MCSA_ELF_TypeFunction);
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} else if (DirectiveID.getString() == ".param" ||
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DirectiveID.getString() == ".local") {
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// Track the number of locals, needed for correct virtual register
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// assignment elsewhere.
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// Also output a directive to the streamer.
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std::vector<MVT> Params;
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std::vector<MVT> Locals;
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while (Lexer.is(AsmToken::Identifier)) {
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auto RegType = ParseRegType(Lexer.getTok().getString());
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if (RegType == MVT::INVALID_SIMPLE_VALUE_TYPE)
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return true;
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if (DirectiveID.getString() == ".param") {
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Params.push_back(RegType);
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} else {
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Locals.push_back(RegType);
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}
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Parser.Lex();
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if (!IsNext(AsmToken::Comma))
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break;
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}
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assert(LastLabel);
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TOut.emitParam(LastLabel, Params);
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TOut.emitLocal(Locals);
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} else {
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// For now, ignore anydirective we don't recognize:
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while (Lexer.isNot(AsmToken::EndOfStatement))
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Parser.Lex();
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}
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return Expect(AsmToken::EndOfStatement, "EOL");
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}
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bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned & /*Opcode*/,
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OperandVector &Operands, MCStreamer &Out,
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uint64_t &ErrorInfo,
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bool MatchingInlineAsm) override {
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MCInst Inst;
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unsigned MatchResult =
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MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm);
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switch (MatchResult) {
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case Match_Success: {
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Out.EmitInstruction(Inst, getSTI());
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return false;
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}
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case Match_MissingFeature:
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return Parser.Error(
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IDLoc, "instruction requires a WASM feature not currently enabled");
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case Match_MnemonicFail:
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return Parser.Error(IDLoc, "invalid instruction");
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case Match_NearMisses:
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return Parser.Error(IDLoc, "ambiguous instruction");
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case Match_InvalidTiedOperand:
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case Match_InvalidOperand: {
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SMLoc ErrorLoc = IDLoc;
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if (ErrorInfo != ~0ULL) {
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if (ErrorInfo >= Operands.size())
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return Parser.Error(IDLoc, "too few operands for instruction");
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ErrorLoc = Operands[ErrorInfo]->getStartLoc();
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if (ErrorLoc == SMLoc())
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ErrorLoc = IDLoc;
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}
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return Parser.Error(ErrorLoc, "invalid operand for instruction");
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}
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}
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llvm_unreachable("Implement any new match types added!");
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}
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};
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} // end anonymous namespace
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// Force static initialization.
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extern "C" void LLVMInitializeWebAssemblyAsmParser() {
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RegisterMCAsmParser<WebAssemblyAsmParser> X(getTheWebAssemblyTarget32());
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RegisterMCAsmParser<WebAssemblyAsmParser> Y(getTheWebAssemblyTarget64());
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}
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#define GET_REGISTER_MATCHER
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#define GET_MATCHER_IMPLEMENTATION
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#include "WebAssemblyGenAsmMatcher.inc"
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