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https://github.com/RPCS3/llvm-mirror.git
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5d83bd89a5
shift counts, and patterns that match dynamic shift counts when the subtract is obscured by a truncate node. Add DAGCombiner support for recognizing rotate patterns when the shift counts are defined by truncate nodes. Fix and simplify the code for commuting shld and shrd instructions to work even when the given instruction doesn't have a parent, and when the caller needs a new instruction. These changes allow LLVM to use the shld, shrd, rol, and ror instructions on x86 to replace equivalent code using two shifts and an or in many more cases. llvm-svn: 57662
74 lines
1.4 KiB
LLVM
74 lines
1.4 KiB
LLVM
; RUN: llvm-as < %s | llc -march=x86-64 > %t
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; RUN: grep rol %t | count 3
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; RUN: grep ror %t | count 1
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; RUN: grep shld %t | count 2
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; RUN: grep shrd %t | count 2
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define i64 @foo(i64 %x, i64 %y, i64 %z) nounwind readnone {
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entry:
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%0 = shl i64 %x, %z
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%1 = sub i64 64, %z
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%2 = lshr i64 %x, %1
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%3 = or i64 %2, %0
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ret i64 %3
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}
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define i64 @bar(i64 %x, i64 %y, i64 %z) nounwind readnone {
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entry:
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%0 = shl i64 %y, %z
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%1 = sub i64 64, %z
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%2 = lshr i64 %x, %1
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%3 = or i64 %2, %0
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ret i64 %3
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}
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define i64 @un(i64 %x, i64 %y, i64 %z) nounwind readnone {
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entry:
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%0 = lshr i64 %x, %z
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%1 = sub i64 64, %z
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%2 = shl i64 %x, %1
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%3 = or i64 %2, %0
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ret i64 %3
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}
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define i64 @bu(i64 %x, i64 %y, i64 %z) nounwind readnone {
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entry:
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%0 = lshr i64 %y, %z
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%1 = sub i64 64, %z
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%2 = shl i64 %x, %1
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%3 = or i64 %2, %0
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ret i64 %3
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}
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define i64 @xfoo(i64 %x, i64 %y, i64 %z) nounwind readnone {
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entry:
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%0 = lshr i64 %x, 57
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%1 = shl i64 %x, 7
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%2 = or i64 %0, %1
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ret i64 %2
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}
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define i64 @xbar(i64 %x, i64 %y, i64 %z) nounwind readnone {
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entry:
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%0 = shl i64 %y, 7
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%1 = lshr i64 %x, 57
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%2 = or i64 %0, %1
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ret i64 %2
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}
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define i64 @xun(i64 %x, i64 %y, i64 %z) nounwind readnone {
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entry:
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%0 = lshr i64 %x, 7
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%1 = shl i64 %x, 57
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%2 = or i64 %0, %1
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ret i64 %2
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}
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define i64 @xbu(i64 %x, i64 %y, i64 %z) nounwind readnone {
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entry:
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%0 = lshr i64 %y, 7
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%1 = shl i64 %x, 57
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%2 = or i64 %0, %1
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ret i64 %2
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}
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