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The SchedModel allows the addition of ReadAdvances to express that certain operands of the instructions are needed at a later point than the others. RegAlloc may add pseudo operands that are not part of the instruction descriptor, and therefore cannot have any read advance entries. This meant that in some cases the desired read advance was nullified by such a pseudo operand, which still had the original latency. This patch fixes this by making sure that such pseudo operands get a zero latency during DAG construction. Review: Matthias Braun, Ulrich Weigand. https://reviews.llvm.org/D49671 llvm-svn: 345606
28 lines
892 B
LLVM
28 lines
892 B
LLVM
; RUN: llc -mtriple thumbv7--windows-itanium -code-model large -verify-machineinstrs -filetype obj -o - %s \
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; RUN: | llvm-objdump -no-show-raw-insn -d - | FileCheck %s
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; ModuleID = 'reduced.c'
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target datalayout = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv7--windows-itanium"
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define arm_aapcs_vfpcc i8 @isel(i32 %i) {
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entry:
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%i.addr = alloca i32, align 4
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%buffer = alloca [4096 x i8], align 1
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store i32 %i, i32* %i.addr, align 4
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%0 = load i32, i32* %i.addr, align 4
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%rem = urem i32 %0, 4096
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%arrayidx = getelementptr inbounds [4096 x i8], [4096 x i8]* %buffer, i32 0, i32 %rem
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%1 = load volatile i8, i8* %arrayidx, align 1
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ret i8 %1
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}
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; CHECK-LABEL: isel
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; CHECK: push {r4, r5, r6, lr}
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; CHECK-DAG: movw r12, #0
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; CHECK-DAG: movt r12, #0
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; CHECK-DAG: movw r4, #{{\d*}}
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; CHECK: blx r12
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; CHECK: sub.w sp, sp, r4
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