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Andrea Di Biagio 0792e8ab30 [X86][BtVer2] correctly model the latency/throughput of LEA instructions.
This patch fixes the latency/throughput of LEA instructions in the BtVer2
scheduling model.

On Jaguar, A 3-operands LEA has a latency of 2cy, and a reciprocal throughput of
1. That is because it uses one cycle of SAGU followed by 1cy of ALU1.  An LEA
with a "Scale" operand is also slow, and it has the same latency profile as the
3-operands LEA. An LEA16r has a latency of 3cy, and a throughput of 0.5 (i.e.
RThrouhgput of 2.0).

This patch adds a new TIIPredicate named IsThreeOperandsLEAFn to X86Schedule.td.
The tablegen backend (for instruction-info) expands that definition into this
(file X86GenInstrInfo.inc):
```
static bool isThreeOperandsLEA(const MachineInstr &MI) {
  return (
    (
      MI.getOpcode() == X86::LEA32r
      || MI.getOpcode() == X86::LEA64r
      || MI.getOpcode() == X86::LEA64_32r
      || MI.getOpcode() == X86::LEA16r
    )
    && MI.getOperand(1).isReg()
    && MI.getOperand(1).getReg() != 0
    && MI.getOperand(3).isReg()
    && MI.getOperand(3).getReg() != 0
    && (
      (
        MI.getOperand(4).isImm()
        && MI.getOperand(4).getImm() != 0
      )
      || (MI.getOperand(4).isGlobal())
    )
  );
}
```

A similar method is generated in the X86_MC namespace, and included into
X86MCTargetDesc.cpp (the declaration lives in X86MCTargetDesc.h).

Back to the BtVer2 scheduling model:
A new scheduling predicate named JSlowLEAPredicate now checks if either the
instruction is a three-operands LEA, or it is an LEA with a Scale value
different than 1.
A variant scheduling class uses that new predicate to correctly select the
appropriate latency profile.

Differential Revision: https://reviews.llvm.org/D49436

llvm-svn: 337469
2018-07-19 16:42:15 +00:00
bindings [LLVM-C] [OCaml] Remove LLVMAddBBVectorizePass 2018-05-28 16:58:10 +00:00
cmake [CMake] Export the LLVM_LINK_LLVM_DYLIB setting 2018-07-18 08:53:31 +00:00
docs [Docs] Testing Debug Info Preservation in Optimizations 2018-07-19 14:08:54 +00:00
examples [ORC] Update JITCompileCallbackManager to support multi-threaded code. 2018-05-30 01:57:45 +00:00
include [ThinLTO] Enable ThinLTO WholeProgramDevirt and LowerTypeTests in new PM 2018-07-19 14:51:32 +00:00
lib [X86][BtVer2] correctly model the latency/throughput of LEA instructions. 2018-07-19 16:42:15 +00:00
projects [cmake] Support moving debuginfo-tests to llvm/projects 2017-12-12 17:06:08 +00:00
resources
runtimes Revert "[CMake] Pass Clang defaults to runtimes builds" 2018-07-13 20:01:55 +00:00
test [X86][BtVer2] correctly model the latency/throughput of LEA instructions. 2018-07-19 16:42:15 +00:00
tools [llvm-readobj] - Do not report invalid amount of sections. 2018-07-19 14:52:57 +00:00
unittests Revert rL337292 due to another MSVC STL problem. 2018-07-17 17:12:50 +00:00
utils Add (very partial) Kate syntax highlighting definition for TableGen 2018-07-18 18:35:27 +00:00
.arcconfig [llvm] Set up .arcconfig to point to Diffusion L repository 2018-01-12 15:37:41 +00:00
.clang-format
.clang-tidy
.gitattributes [DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label. 2018-05-09 02:40:45 +00:00
.gitignore gitignore: Ignore .vs folder (VS2017 config files) 2017-04-08 00:16:58 +00:00
CMakeLists.txt [CMake] Teach the build system to codesign built products 2018-07-10 17:32:48 +00:00
CODE_OWNERS.TXT CODE_OWNERS: Take ownership of the MIPS backend 2018-06-21 09:59:44 +00:00
configure
CREDITS.TXT Update my information in the CREDITS file. 2018-06-15 20:02:11 +00:00
LICENSE.TXT Update copyright year to 2018. 2018-06-18 12:22:17 +00:00
llvm.spec.in
LLVMBuild.txt
README.txt Test commit: remove a blank line 2018-06-08 21:21:55 +00:00
RELEASE_TESTERS.TXT Remove myself from the release testers list. (NFC) 2018-06-20 21:25:50 +00:00

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