Colin LeMahieu 07e42127a4 [Hexagon] Adding sub/and/or reg, imm forms ... llvm-svn: 223522		2014-12-05 21:38:29 +00:00
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AArch64
ARM	Add support for ARM modified-immediate assembly syntax.	2014-12-02 10:53:20 +00:00
Hexagon	[Hexagon] Adding sub/and/or reg, imm forms	2014-12-05 21:38:29 +00:00
Mips	The andi16, addiusp and jraddiusp micromips instructions were missing dedicated decoder methods in MipsDisassembler.cpp to properly decode immediate operands. These methods are added together with corresponding tests.	2014-12-01 11:12:04 +00:00
PowerPC	[PowerPC] Add asm support for cache-inhibited ld/st instructions	2014-11-30 10:15:56 +00:00
Sparc
SystemZ
X86	AVX-512: Fixed encoding of VPBROADCASTM and added SKX forms of this instruction	2014-10-26 09:52:24 +00:00
XCore