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Thomas Lively da6e144269 [WebAssembly] vNxM.load_splat instructions 
Summary:
Adds the new load_splat instructions as specified at
https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#load-and-splat.

DAGISel does not allow matching multiple copies of the same load in a
single pattern, so we use a new node in WebAssemblyISD to wrap loads
that should be splatted.

Depends on D67783.

Reviewers: aheejin

Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67784

llvm-svn: 372655
2019-09-23 20:42:12 +00:00
..
AArch64
AArch64: support arm64_32, an ILP32 slice for watchOS.
2019-09-12 10:22:23 +00:00
AMDGPU
[AMDGPU][MC] Corrected handling of relocatable expressions
2019-09-23 15:41:51 +00:00
ARM
[ARM] VFPv2 only supports 16 D registers.
2019-09-17 21:42:38 +00:00
AsmParser
Remove some unnecessary REQUIRES: shell lines
2019-09-10 00:06:52 +00:00
AVR
…
BPF
…
COFF
[X86] Print register names in .seh_* directives
2019-08-30 21:23:05 +00:00
Disassembler
[SystemZ] Support z15 processor name
2019-09-20 23:04:45 +00:00
ELF
Remove some unnecessary REQUIRES: shell lines
2019-09-10 00:06:52 +00:00
Hexagon
[llvm-mc] Add reportWarning() to MCContext
2019-08-08 19:13:23 +00:00
Lanai
…
MachO
[MachO][TLOF] Use hasLocalLinkage to determine if indirect symbol is local
2019-08-22 16:59:00 +00:00
Mips
[mips] Expand 'lw/sw' instructions for 32-bit GOT
2019-09-18 19:19:47 +00:00
MSP430
…
PowerPC
[PowerPC] Support extended mnemonics mffprwz etc.
2019-08-29 21:53:59 +00:00
RISCV
[RISCV] Support llvm-objdump -M no-aliases and -M numeric
2019-09-10 16:24:03 +00:00
Sparc
…
SystemZ
[SystemZ] Support z15 processor name
2019-09-20 23:04:45 +00:00
WebAssembly
[WebAssembly] vNxM.load_splat instructions
2019-09-23 20:42:12 +00:00
X86
[MC] Pass through .code16/32/64 and .syntax unified for COFF
2019-09-03 18:16:52 +00:00