mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2025-02-04 11:17:31 +00:00
ccb96c68e1
In Thumb2, instructions which write to the PC are UNPREDICTABLE if they are in an IT block but not the last instruction in the block. Previously, we only diagnosed this for LDM instructions, this patch extends the diagnostic to cover all of the relevant instructions. Differential Revision: https://reviews.llvm.org/D30398 llvm-svn: 296459
27 lines
1.0 KiB
ArmAsm
27 lines
1.0 KiB
ArmAsm
@ RUN: not llvm-mc -triple=thumbv7-apple-darwin -mcpu=cortex-a8 -show-encoding -mattr=-trustzone < %s | FileCheck %s -check-prefix=NOTZ
|
|
@ RUN: llvm-mc -triple=thumbv7-apple-darwin -mcpu=cortex-a8 -show-encoding -mattr=trustzone < %s | FileCheck %s -check-prefix=TZ
|
|
@ RUN: not llvm-mc -triple=thumbv6kz -mcpu=arm1176jzf-s -show-encoding < %s | FileCheck %s -check-prefix=NOTZ
|
|
|
|
.syntax unified
|
|
.globl _func
|
|
|
|
@ Check that the assembler processes SMC instructions when TrustZone support is
|
|
@ active and that it rejects them when this feature is not enabled
|
|
|
|
_func:
|
|
@ CHECK: _func
|
|
|
|
|
|
@------------------------------------------------------------------------------
|
|
@ SMC
|
|
@------------------------------------------------------------------------------
|
|
smc #0xf
|
|
it eq
|
|
smceq #0
|
|
|
|
@ NOTZ-NOT: smc #15
|
|
@ NOTZ-NOT: smceq #0
|
|
@ TZ: smc #15 @ encoding: [0xff,0xf7,0x00,0x80]
|
|
@ TZ: it eq @ encoding: [0x08,0xbf]
|
|
@ TZ: smceq #0 @ encoding: [0xf0,0xf7,0x00,0x80]
|