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This lowering tries to look for G_PTR_ADD instructions and then converts them to a standard G_ADD with a COPY on the source, and G_INTTOPTR on the result. This is ok for address space 0 on AArch64 as p0 can be treated as s64. The motivation behind this is to expose the add semantics to the imported tablegen patterns. We shouldn't need to check for uses being loads/stores, because the selector works bottom up, uses before defs. By the time we end up trying to select a G_PTR_ADD, we should have already attempted to fold this into addressing modes and were therefore unsuccessful. This gives some performance and code size improvements across the board. Differential Revision: https://reviews.llvm.org/D73673
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