mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2025-04-03 00:01:39 +00:00
1311b33688
Summary: This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between SETcc instructions and condition codes. Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser. Reviewers: andreadb, courbet, RKSimon, spatel, lebedev.ri Reviewed By: andreadb Subscribers: hiraditya, lebedev.ri, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60138 llvm-svn: 357801
87 lines
2.9 KiB
TableGen
87 lines
2.9 KiB
TableGen
//===-- X86SchedPredicates.td - X86 Scheduling Predicates --*- tablegen -*-===//
|
|
//
|
|
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
|
// See https://llvm.org/LICENSE.txt for license information.
|
|
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file defines scheduling predicate definitions that are common to
|
|
// all X86 subtargets.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// A predicate used to identify dependency-breaking instructions that clear the
|
|
// content of the destination register. Note that this predicate only checks if
|
|
// input registers are the same. This predicate doesn't make any assumptions on
|
|
// the expected instruction opcodes, because different processors may implement
|
|
// different zero-idioms.
|
|
def ZeroIdiomPredicate : CheckSameRegOperand<1, 2>;
|
|
|
|
// A predicate used to identify VPERM that have bits 3 and 7 of their mask set.
|
|
// On some processors, these VPERM instructions are zero-idioms.
|
|
def ZeroIdiomVPERMPredicate : CheckAll<[
|
|
ZeroIdiomPredicate,
|
|
CheckImmOperand<3, 0x88>
|
|
]>;
|
|
|
|
// A predicate used to check if a LEA instruction uses all three source
|
|
// operands: base, index, and offset.
|
|
def IsThreeOperandsLEAPredicate: CheckAll<[
|
|
// isRegOperand(Base)
|
|
CheckIsRegOperand<1>,
|
|
CheckNot<CheckInvalidRegOperand<1>>,
|
|
|
|
// isRegOperand(Index)
|
|
CheckIsRegOperand<3>,
|
|
CheckNot<CheckInvalidRegOperand<3>>,
|
|
|
|
// hasLEAOffset(Offset)
|
|
CheckAny<[
|
|
CheckAll<[
|
|
CheckIsImmOperand<4>,
|
|
CheckNot<CheckZeroOperand<4>>
|
|
]>,
|
|
CheckNonPortable<"MI.getOperand(4).isGlobal()">
|
|
]>
|
|
]>;
|
|
|
|
def LEACases : MCOpcodeSwitchCase<
|
|
[LEA32r, LEA64r, LEA64_32r, LEA16r],
|
|
MCReturnStatement<IsThreeOperandsLEAPredicate>
|
|
>;
|
|
|
|
// Used to generate the body of a TII member function.
|
|
def IsThreeOperandsLEABody :
|
|
MCOpcodeSwitchStatement<[LEACases], MCReturnStatement<FalsePred>>;
|
|
|
|
// This predicate evaluates to true only if the input machine instruction is a
|
|
// 3-operands LEA. Tablegen automatically generates a new method for it in
|
|
// X86GenInstrInfo.
|
|
def IsThreeOperandsLEAFn :
|
|
TIIPredicate<"isThreeOperandsLEA", IsThreeOperandsLEABody>;
|
|
|
|
// A predicate to check for COND_A and COND_BE CMOVs which have an extra uop
|
|
// on recent Intel CPUs.
|
|
def IsCMOVArr_Or_CMOVBErr : CheckAny<[
|
|
CheckImmOperand_s<3, "X86::COND_A">,
|
|
CheckImmOperand_s<3, "X86::COND_BE">
|
|
]>;
|
|
|
|
def IsCMOVArm_Or_CMOVBErm : CheckAny<[
|
|
CheckImmOperand_s<7, "X86::COND_A">,
|
|
CheckImmOperand_s<7, "X86::COND_BE">
|
|
]>;
|
|
|
|
// A predicate to check for COND_A and COND_BE SETCCs which have an extra uop
|
|
// on recent Intel CPUs.
|
|
def IsSETAr_Or_SETBEr : CheckAny<[
|
|
CheckImmOperand_s<1, "X86::COND_A">,
|
|
CheckImmOperand_s<1, "X86::COND_BE">
|
|
]>;
|
|
|
|
def IsSETAm_Or_SETBEm : CheckAny<[
|
|
CheckImmOperand_s<5, "X86::COND_A">,
|
|
CheckImmOperand_s<5, "X86::COND_BE">
|
|
]>;
|