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Alex Bradbury 148dfff3f8 [RISCV] Implement assembler pseudo instructions for RV32I and RV64I

Adds the assembler pseudo instructions of RV32I and RV64I which can
be mapped to a single canonical instruction. The missing pseudo
instructions (e.g., call, tail, ...) are marked as TODO. Other
things, like for example PCREL_LO, have to be implemented first.

Currently, alias emission is disabled by default to keep the patch
minimal. Alias emission by default will be enabled in a subsequent
patch which also updates all affected tests. Note that this patch
should actually break the floating point MC tests. However, the
used FileCheck configuration is not tight enought to detect the
breakage.

Differential Revision: https://reviews.llvm.org/D40902

Patch by Mario Werner.

llvm-svn: 320487

2017-12-12 15:46:15 +00:00

AArch64

[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.

2017-12-07 10:40:31 +00:00

AMDGPU

[AMDGPU][MC][GFX9] Corrected encoding of ttmp registers, disabled tba/tma

2017-12-11 15:23:20 +00:00

ARM

[DWARFv5] Emit v5 line table header.

2017-12-05 20:35:00 +00:00

AsmParser

[CodeGen] Unify MBB reference format in both MIR and debug output