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- Add a target-specific DAG optimization to recognize a pattern PTEST-able. Such a pattern is a OR'd tree with X86ISD::OR as the root node. When X86ISD::OR node has only its flag result being used as a boolean value and all its leaves are extracted from the same vector, it could be folded into an X86ISD::PTEST node. llvm-svn: 162735 |
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ARM | ||
CellSPU | ||
CPP | ||
Generic | ||
Hexagon | ||
MBlaze | ||
Mips | ||
MSP430 | ||
NVPTX | ||
PowerPC | ||
SPARC | ||
Thumb | ||
Thumb2 | ||
X86 | ||
XCore |