Igor Breger 1ff2ecf610 Fixed a bug in type legalizer for masked gather. ...

The problem occurs when the Node doesn't updated in place , UpdateNodeOperation() return the node that already exist.
In this case assert fail in PromoteIntegerOperand() , N have 2 results ( val + chain).

Differential Revision: http://reviews.llvm.org/D23756

llvm-svn: 279961

2016-08-29 09:12:31 +00:00

..

AArch64

[GlobalISel] Add a fallback path to SDISel.

2016-08-27 00:18:31 +00:00

AMDGPU

AMDGPU/R600: Enable Load combine

2016-08-27 19:09:43 +00:00

ARM

Handle empty functions with debug info in load/store opt pass

2016-08-26 13:00:39 +00:00

BPF

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Generic

CodeGen: Remove MachineFunctionAnalysis => Enable (Machine)ModulePasses

2016-08-24 01:52:46 +00:00

Hexagon

[Hexagon] vector store print tracing.

2016-08-25 13:35:48 +00:00

Inputs

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Lanai

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Mips

[mips] Preparatory work for a generic scheduler

2016-08-24 13:00:47 +00:00

MIR

MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it

2016-08-25 01:27:13 +00:00

MSP430

Revert r279242 - it's failing the tests

2016-08-19 14:18:34 +00:00

NVPTX

[NVPTX] Switch nvptx-use-infer-addrspace to true.

2016-08-19 20:46:45 +00:00

PowerPC

[PowerPC] Implement lowering for atomicrmw min/max/umin/umax

2016-08-28 16:17:58 +00:00

SPARC

Revert "[Sparc] Leon errata fix passes."

2016-08-12 14:48:09 +00:00

SystemZ

[SystemZ] Use valid base/index regs for inline asm

2016-08-18 21:44:15 +00:00

Thumb

[ARM] Generate consistent frame records for Thumb2

2016-08-23 09:19:22 +00:00

Thumb2

CodeGen: If Convert blocks that would form a diamond when tail-merged.

2016-08-24 21:34:27 +00:00

WebAssembly

[WebAssembly] Disable the store-results optimization.

2016-08-18 17:51:27 +00:00

WinEH

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X86

Fixed a bug in type legalizer for masked gather.

2016-08-29 09:12:31 +00:00

XCore

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