Jakob Stoklund Olesen 924b84cf0f Teach VirtRegRewriter to handle spilling in instructions that have multiple
definitions of the virtual register.

This happens when spilling the registers produced by REG_SEQUENCE:

%reg1047:5<def>, %reg1047:6<def>, %reg1047:7<def> = VLD3d8 %reg1033, 0, pred:14, pred:%reg0

The rewriter would spill the register multiple times, dead store elimination
tried to keep up, but ended up cutting the branch it was sitting on.

llvm-svn: 104321
2010-05-21 16:36:13 +00:00
..
2010-04-26 21:37:43 +00:00
2010-05-20 00:07:13 +00:00
2010-03-10 18:41:59 +00:00