Dan Gohman 8c835f6285 Disable the register+memory forms of the bt instructions for now. Thanks ...

to Eli for pointing out that these forms don't ignore the high bits of
their index operands, and as such are not immediately suitable for use
by isel.

llvm-svn: 62194

2009-01-13 23:23:30 +00:00

..

Alpha

Correct some thinkos in the expansion of ADD/SUB

2008-11-12 08:23:26 +00:00

ARM

Clean up some ARM GV asm printing out; minor fixes to match what gcc does.

2008-12-06 02:00:55 +00:00

CBackend

Fix PR2907 by digging through constant expressions to find FP constants that

2008-10-22 04:53:16 +00:00

CellSPU

Fix off-by-one error in traversing an array; this fixes a test.

2009-01-07 23:07:29 +00:00

CPP

…

Generic

The list-td and list-tdrr schedulers don't yet support physreg

2009-01-13 20:24:13 +00:00

IA64

…

Mips

The list-td and list-tdrr schedulers don't yet support physreg

2009-01-13 20:24:13 +00:00

PowerPC

this test should not run opt -std-compile-opts, it should run

2009-01-09 05:32:00 +00:00

SPARC

…

X86

Disable the register+memory forms of the bt instructions for now. Thanks

2009-01-13 23:23:30 +00:00

XCore

Add support for ISD::TRAP to the XCore backend

2008-12-03 10:59:16 +00:00