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llvm-mirror/test/CodeGen
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Scott Constable 89f19db618 [X86] Add RET-hardening Support to mitigate Load Value Injection (LVI) 
Adding a pass that replaces every ret instruction with the sequence:

pop <scratch-reg>
lfence
jmp *<scratch-reg>

where <scratch-reg> is some available scratch register, according to the
calling convention of the function being mitigated.

Differential Revision: https://reviews.llvm.org/D75935
2020-04-03 12:08:34 -07:00
..
AArch64 [AArch64] Fix swap-compare-operands test names to fix issue reported on D77354 2020-04-03 17:48:18 +01:00
AMDGPU [AMDGPU] Added label to test. NFC. 2020-04-03 11:36:32 -07:00
ARC
ARM [NFC] Move ARM opt -indvars test from Codegen into Transforms 2020-04-03 20:15:03 +03:00
AVR [AVR] Generalize the previous interrupt bugfix to signal handlers too 2020-03-31 19:33:34 +13:00
BPF [BPF] support 128bit int explicitly in layout spec 2020-03-28 11:46:29 -07:00
Generic [X86] Move combineLoopMAddPattern and combineLoopSADPattern to an IR pass before SelecitonDAG. 2020-03-26 14:10:20 -07:00
Hexagon Revert "Include static prof data when collecting loop BBs" 2020-03-24 09:41:16 -07:00
Inputs
Lanai
Mips [Mips] Make MipsBranchExpansion aware of BBIT family of branch 2020-03-31 09:20:51 +02:00
MIR AMDGPU: Assume f32 denormals are enabled by default 2020-04-02 17:17:12 -04:00
MSP430
NVPTX [DAGCombiner] Require ninf for sqrt recip estimation 2020-04-01 16:23:43 +08:00
PowerPC [PowerPC] Regenerate f128 test to fix issue reported on D77354 2020-04-03 17:01:28 +01:00
RISCV [LegalizeTypes][RISCV] Correctly sign-extend comparison for ATOMIC_CMP_XCHG 2020-04-01 15:51:26 +01:00
SPARC
SystemZ [LoopDataPrefetch + SystemZ] Let target decide on prefetching for each loop. 2020-04-02 14:57:46 +02:00
Thumb [DAGCombine] Skip PostInc combine with later users 2020-03-23 08:39:53 +00:00
Thumb2 [ARM] Fix incorrect handling of big-endian vmov.i64 2020-04-03 17:36:50 +01:00
VE
WebAssembly [WebAssembly] EmscriptenEHSjLj: Mark __invoke_ functions as imported 2020-04-01 16:33:33 -07:00
WinCFGuard
WinEH
X86 [X86] Add RET-hardening Support to mitigate Load Value Injection (LVI) 2020-04-03 12:08:34 -07:00
XCore