Tom Stellard 3b9645302a R600/SI: Use VSrc_* register classes as the default classes for types ... Since the VSrc_* register classes contain both VGPRs and SGPRs, copies that used be emitted by isel like this: SGPR = COPY VGPR Will now be emitted like this: VSrC = COPY VGPR This patch also adds a pass that tries to identify and fix situations where a VGPR to SGPR copy may occur. Hopefully, these changes will make it impossible for the compiler to generate illegal VGPR to SGPR copies. llvm-svn: 187831		2013-08-06 23:08:28 +00:00
..
AArch64	AArch64: add initial NEON support	2013-08-01 09:20:35 +00:00
ARM	Debug Info Finder|Verifier: handle DbgLoc attached to instructions.	2013-08-06 19:38:43 +00:00
CPP
Generic	Debug Info: clean up usage of Verify.	2013-06-28 05:43:10 +00:00
Hexagon	Refactor isInTailCallPosition handling	2013-08-06 09:12:35 +00:00
Inputs	Debug Info Verifier: verify SPs in llvm.dbg.sp.	2013-07-27 01:26:08 +00:00
Mips	Add the saving of S2. This is needed for some of the floating point	2013-08-04 23:56:53 +00:00
MSP430	Use conventional syntax for branches.	2013-07-14 18:19:44 +00:00
NVPTX	[NVPTX] Add missing patterns for i1 [s,u]int_to_fp	2013-08-06 14:13:34 +00:00
PowerPC	Add PPC64 mulli pattern	2013-08-06 17:03:03 +00:00
R600	R600/SI: Use VSrc_* register classes as the default classes for types	2013-08-06 23:08:28 +00:00
SI
SPARC	Allocate local registers in order for optimal coloring.	2013-07-25 18:35:14 +00:00
SystemZ	[SystemZ] Use BRCT and BRCTG to eliminate add-&-compare sequences	2013-08-05 11:23:46 +00:00
Thumb	Debug Info: update testing cases to pass verifier.	2013-07-29 18:12:58 +00:00
Thumb2	Refactor AnalyzeBranch on ARM. The previous version did not always analyze	2013-07-19 23:52:47 +00:00
X86	Debug Info Finder|Verifier: handle DbgLoc attached to instructions.	2013-08-06 19:38:43 +00:00
XCore	XCore target: Fix Vararg handling	2013-08-01 08:29:44 +00:00