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b51c27cd9a
masks to match inversely for the code as is to work. For the example given we actually want: bfi r0, r2, #1, #1 not #0, however, given the way the pattern is written it's not possible at the moment. Fixes rdar://9177502 llvm-svn: 128320
63 lines
1.7 KiB
LLVM
63 lines
1.7 KiB
LLVM
; RUN: llc -march=thumb -mattr=+v6t2 < %s | FileCheck %s
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%struct.F = type { [3 x i8], i8 }
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@X = common global %struct.F zeroinitializer, align 4 ; <%struct.F*> [#uses=1]
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define void @f1([1 x i32] %f.coerce0) nounwind {
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entry:
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; CHECK: f1
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; CHECK: movs r2, #10
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; CHECK: bfi r1, r2, #22, #4
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%0 = load i32* bitcast (%struct.F* @X to i32*), align 4 ; <i32> [#uses=1]
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%1 = and i32 %0, -62914561 ; <i32> [#uses=1]
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%2 = or i32 %1, 41943040 ; <i32> [#uses=1]
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store i32 %2, i32* bitcast (%struct.F* @X to i32*), align 4
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ret void
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}
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define i32 @f2(i32 %A, i32 %B) nounwind readnone optsize {
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entry:
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; CHECK: f2
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; CHECK: lsrs r1, r1, #7
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; CHECK: bfi r0, r1, #7, #16
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%and = and i32 %A, -8388481 ; <i32> [#uses=1]
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%and2 = and i32 %B, 8388480 ; <i32> [#uses=1]
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%or = or i32 %and2, %and ; <i32> [#uses=1]
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ret i32 %or
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}
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define i32 @f3(i32 %A, i32 %B) nounwind readnone optsize {
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entry:
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; CHECK: f3
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; CHECK: lsrs r2, r0, #7
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; CHECK: mov r0, r1
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; CHECK: bfi r0, r2, #7, #16
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%and = and i32 %A, 8388480 ; <i32> [#uses=1]
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%and2 = and i32 %B, -8388481 ; <i32> [#uses=1]
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%or = or i32 %and2, %and ; <i32> [#uses=1]
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ret i32 %or
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}
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; rdar://8752056
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define i32 @f4(i32 %a) nounwind {
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; CHECK: f4
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; CHECK: movw r1, #3137
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; CHECK: bfi r1, r0, #15, #5
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%1 = shl i32 %a, 15
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%ins7 = and i32 %1, 1015808
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%ins12 = or i32 %ins7, 3137
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ret i32 %ins12
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}
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; rdar://9177502
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define i32 @f5(i32 %a, i32 %b) nounwind readnone {
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entry:
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; CHECK f5
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; CHECK-NOT: bfi r0, r2, #0, #1
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%and = and i32 %a, 2
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%b.masked = and i32 %b, -2
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%and3 = or i32 %b.masked, %and
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ret i32 %and3
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}
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