Evan Cheng c52f942d67 Do not isel load folding bt instructions for pentium m, core, core2, and AMD processors. These are significantly slower than a load followed by a bt of a register. ...

llvm-svn: 61557

2009-01-02 05:35:45 +00:00

..

Alpha

Correct some thinkos in the expansion of ADD/SUB

2008-11-12 08:23:26 +00:00

ARM

Clean up some ARM GV asm printing out; minor fixes to match what gcc does.

2008-12-06 02:00:55 +00:00

CBackend

Fix PR2907 by digging through constant expressions to find FP constants that

2008-10-22 04:53:16 +00:00

CellSPU

Fix PR3274: when promoting the condition of a BRCOND node,

2009-01-01 15:52:00 +00:00

CPP

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Generic

Revert the changes in this testcase until Anton can fix them.

2008-12-24 05:23:34 +00:00

IA64

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Mips

Fix PR2667: add soft float support for sint_to_fp/uint_to_fp

2008-11-10 17:36:26 +00:00

PowerPC

rename a file to follow naming conventions.

2009-01-02 01:52:35 +00:00

SPARC

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X86

Do not isel load folding bt instructions for pentium m, core, core2, and AMD processors. These are significantly slower than a load followed by a bt of a register.

2009-01-02 05:35:45 +00:00

XCore

Add support for ISD::TRAP to the XCore backend

2008-12-03 10:59:16 +00:00