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2d87a43549
llvm-svn: 114273
1080 lines
35 KiB
C++
1080 lines
35 KiB
C++
//===------ RegAllocPBQP.cpp ---- PBQP Register Allocator -------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a Partitioned Boolean Quadratic Programming (PBQP) based
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// register allocator for LLVM. This allocator works by constructing a PBQP
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// problem representing the register allocation problem under consideration,
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// solving this using a PBQP solver, and mapping the solution back to a
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// register assignment. If any variables are selected for spilling then spill
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// code is inserted and the process repeated.
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//
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// The PBQP solver (pbqp.c) provided for this allocator uses a heuristic tuned
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// for register allocation. For more information on PBQP for register
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// allocation, see the following papers:
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//
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// (1) Hames, L. and Scholz, B. 2006. Nearly optimal register allocation with
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// PBQP. In Proceedings of the 7th Joint Modular Languages Conference
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// (JMLC'06). LNCS, vol. 4228. Springer, New York, NY, USA. 346-361.
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//
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// (2) Scholz, B., Eckstein, E. 2002. Register allocation for irregular
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// architectures. In Proceedings of the Joint Conference on Languages,
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// Compilers and Tools for Embedded Systems (LCTES'02), ACM Press, New York,
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// NY, USA, 139-148.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "regalloc"
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#include "RenderMachineFunction.h"
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#include "Splitter.h"
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#include "VirtRegMap.h"
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#include "VirtRegRewriter.h"
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#include "llvm/CodeGen/CalcSpillWeights.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/LiveStackAnalysis.h"
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#include "llvm/CodeGen/RegAllocPBQP.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/PBQP/HeuristicSolver.h"
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#include "llvm/CodeGen/PBQP/Graph.h"
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#include "llvm/CodeGen/PBQP/Heuristics/Briggs.h"
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#include "llvm/CodeGen/RegAllocRegistry.h"
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#include "llvm/CodeGen/RegisterCoalescer.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include <limits>
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#include <memory>
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#include <set>
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#include <vector>
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namespace llvm {
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using namespace PBQP;
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using namespace PBQP::Heuristics;
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static RegisterRegAlloc
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registerPBQPRepAlloc("pbqp", "PBQP register allocator",
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llvm::createPBQPRegisterAllocator);
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static cl::opt<bool>
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pbqpCoalescing("pbqp-coalescing",
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cl::desc("Attempt coalescing during PBQP register allocation."),
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cl::init(false), cl::Hidden);
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static cl::opt<bool>
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pbqpBuilder("pbqp-builder",
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cl::desc("Use new builder system."),
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cl::init(false), cl::Hidden);
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static cl::opt<bool>
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pbqpPreSplitting("pbqp-pre-splitting",
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cl::desc("Pre-splite before PBQP register allocation."),
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cl::init(false), cl::Hidden);
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char RegAllocPBQP::ID = 0;
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unsigned PBQPRAProblem::getVRegForNode(PBQP::Graph::ConstNodeItr node) const {
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Node2VReg::const_iterator vregItr = node2VReg.find(node);
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assert(vregItr != node2VReg.end() && "No vreg for node.");
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return vregItr->second;
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}
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PBQP::Graph::NodeItr PBQPRAProblem::getNodeForVReg(unsigned vreg) const {
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VReg2Node::const_iterator nodeItr = vreg2Node.find(vreg);
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assert(nodeItr != vreg2Node.end() && "No node for vreg.");
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return nodeItr->second;
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}
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const PBQPRAProblem::AllowedSet&
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PBQPRAProblem::getAllowedSet(unsigned vreg) const {
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AllowedSetMap::const_iterator allowedSetItr = allowedSets.find(vreg);
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assert(allowedSetItr != allowedSets.end() && "No pregs for vreg.");
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const AllowedSet &allowedSet = allowedSetItr->second;
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return allowedSet;
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}
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unsigned PBQPRAProblem::getPRegForOption(unsigned vreg, unsigned option) const {
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assert(isPRegOption(vreg, option) && "Not a preg option.");
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const AllowedSet& allowedSet = getAllowedSet(vreg);
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assert(option <= allowedSet.size() && "Option outside allowed set.");
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return allowedSet[option - 1];
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}
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std::auto_ptr<PBQPRAProblem> PBQPBuilder::build(
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MachineFunction *mf,
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const LiveIntervals *lis,
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const RegSet &vregs) {
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typedef std::vector<const LiveInterval*> LIVector;
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MachineRegisterInfo *mri = &mf->getRegInfo();
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const TargetRegisterInfo *tri = mf->getTarget().getRegisterInfo();
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std::auto_ptr<PBQPRAProblem> p(new PBQPRAProblem());
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PBQP::Graph &g = p->getGraph();
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RegSet pregs;
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// Collect the set of preg intervals, record that they're used in the MF.
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for (LiveIntervals::const_iterator itr = lis->begin(), end = lis->end();
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itr != end; ++itr) {
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if (TargetRegisterInfo::isPhysicalRegister(itr->first)) {
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pregs.insert(itr->first);
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mri->setPhysRegUsed(itr->first);
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}
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}
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BitVector reservedRegs = tri->getReservedRegs(*mf);
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// Iterate over vregs.
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for (RegSet::const_iterator vregItr = vregs.begin(), vregEnd = vregs.end();
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vregItr != vregEnd; ++vregItr) {
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unsigned vreg = *vregItr;
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const TargetRegisterClass *trc = mri->getRegClass(vreg);
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const LiveInterval *vregLI = &lis->getInterval(vreg);
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// Compute an initial allowed set for the current vreg.
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typedef std::vector<unsigned> VRAllowed;
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VRAllowed vrAllowed;
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for (TargetRegisterClass::iterator aoItr = trc->allocation_order_begin(*mf),
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aoEnd = trc->allocation_order_end(*mf);
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aoItr != aoEnd; ++aoItr) {
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unsigned preg = *aoItr;
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if (!reservedRegs.test(preg)) {
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vrAllowed.push_back(preg);
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}
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}
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// Remove any physical registers which overlap.
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for (RegSet::const_iterator pregItr = pregs.begin(),
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pregEnd = pregs.end();
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pregItr != pregEnd; ++pregItr) {
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unsigned preg = *pregItr;
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const LiveInterval *pregLI = &lis->getInterval(preg);
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if (pregLI->empty())
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continue;
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if (!vregLI->overlaps(*pregLI))
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continue;
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// Remove the register from the allowed set.
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VRAllowed::iterator eraseItr =
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std::find(vrAllowed.begin(), vrAllowed.end(), preg);
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if (eraseItr != vrAllowed.end()) {
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vrAllowed.erase(eraseItr);
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}
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// Also remove any aliases.
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const unsigned *aliasItr = tri->getAliasSet(preg);
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if (aliasItr != 0) {
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for (; *aliasItr != 0; ++aliasItr) {
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VRAllowed::iterator eraseItr =
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std::find(vrAllowed.begin(), vrAllowed.end(), *aliasItr);
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if (eraseItr != vrAllowed.end()) {
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vrAllowed.erase(eraseItr);
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}
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}
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}
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}
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// Construct the node.
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PBQP::Graph::NodeItr node =
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g.addNode(PBQP::Vector(vrAllowed.size() + 1, 0));
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// Record the mapping and allowed set in the problem.
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p->recordVReg(vreg, node, vrAllowed.begin(), vrAllowed.end());
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PBQP::PBQPNum spillCost = (vregLI->weight != 0.0) ?
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vregLI->weight : std::numeric_limits<PBQP::PBQPNum>::min();
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addSpillCosts(g.getNodeCosts(node), spillCost);
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}
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for (RegSet::const_iterator vr1Itr = vregs.begin(), vrEnd = vregs.end();
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vr1Itr != vrEnd; ++vr1Itr) {
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unsigned vr1 = *vr1Itr;
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const LiveInterval &l1 = lis->getInterval(vr1);
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const PBQPRAProblem::AllowedSet &vr1Allowed = p->getAllowedSet(vr1);
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for (RegSet::iterator vr2Itr = llvm::next(vr1Itr);
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vr2Itr != vrEnd; ++vr2Itr) {
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unsigned vr2 = *vr2Itr;
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const LiveInterval &l2 = lis->getInterval(vr2);
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const PBQPRAProblem::AllowedSet &vr2Allowed = p->getAllowedSet(vr2);
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assert(!l2.empty() && "Empty interval in vreg set?");
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if (l1.overlaps(l2)) {
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PBQP::Graph::EdgeItr edge =
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g.addEdge(p->getNodeForVReg(vr1), p->getNodeForVReg(vr2),
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PBQP::Matrix(vr1Allowed.size()+1, vr2Allowed.size()+1, 0));
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addInterferenceCosts(g.getEdgeCosts(edge), vr1Allowed, vr2Allowed, tri);
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}
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}
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}
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return p;
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}
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void PBQPBuilder::addSpillCosts(PBQP::Vector &costVec,
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PBQP::PBQPNum spillCost) {
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costVec[0] = spillCost;
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}
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void PBQPBuilder::addInterferenceCosts(PBQP::Matrix &costMat,
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const PBQPRAProblem::AllowedSet &vr1Allowed,
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const PBQPRAProblem::AllowedSet &vr2Allowed,
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const TargetRegisterInfo *tri) {
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assert(costMat.getRows() == vr1Allowed.size() + 1 && "Matrix height mismatch.");
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assert(costMat.getCols() == vr2Allowed.size() + 1 && "Matrix width mismatch.");
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for (unsigned i = 0; i < vr1Allowed.size(); ++i) {
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unsigned preg1 = vr1Allowed[i];
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for (unsigned j = 0; j < vr2Allowed.size(); ++j) {
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unsigned preg2 = vr2Allowed[j];
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if (tri->regsOverlap(preg1, preg2)) {
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costMat[i + 1][j + 1] = std::numeric_limits<PBQP::PBQPNum>::infinity();
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}
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}
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}
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}
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void RegAllocPBQP::getAnalysisUsage(AnalysisUsage &au) const {
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au.addRequired<SlotIndexes>();
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au.addPreserved<SlotIndexes>();
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au.addRequired<LiveIntervals>();
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//au.addRequiredID(SplitCriticalEdgesID);
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au.addRequired<RegisterCoalescer>();
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au.addRequired<CalculateSpillWeights>();
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au.addRequired<LiveStacks>();
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au.addPreserved<LiveStacks>();
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au.addRequired<MachineLoopInfo>();
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au.addPreserved<MachineLoopInfo>();
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if (pbqpPreSplitting)
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au.addRequired<LoopSplitter>();
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au.addRequired<VirtRegMap>();
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au.addRequired<RenderMachineFunction>();
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MachineFunctionPass::getAnalysisUsage(au);
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}
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template <typename RegContainer>
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PBQP::Vector RegAllocPBQP::buildCostVector(unsigned vReg,
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const RegContainer &allowed,
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const CoalesceMap &coalesces,
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PBQP::PBQPNum spillCost) const {
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typedef typename RegContainer::const_iterator AllowedItr;
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// Allocate vector. Additional element (0th) used for spill option
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PBQP::Vector v(allowed.size() + 1, 0);
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v[0] = spillCost;
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// Iterate over the allowed registers inserting coalesce benefits if there
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// are any.
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unsigned ai = 0;
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for (AllowedItr itr = allowed.begin(), end = allowed.end();
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itr != end; ++itr, ++ai) {
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unsigned pReg = *itr;
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CoalesceMap::const_iterator cmItr =
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coalesces.find(RegPair(vReg, pReg));
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// No coalesce - on to the next preg.
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if (cmItr == coalesces.end())
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continue;
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// We have a coalesce - insert the benefit.
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v[ai + 1] = -cmItr->second;
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}
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return v;
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}
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template <typename RegContainer>
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PBQP::Matrix* RegAllocPBQP::buildInterferenceMatrix(
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const RegContainer &allowed1, const RegContainer &allowed2) const {
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typedef typename RegContainer::const_iterator RegContainerIterator;
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// Construct a PBQP matrix representing the cost of allocation options. The
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// rows and columns correspond to the allocation options for the two live
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// intervals. Elements will be infinite where corresponding registers alias,
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// since we cannot allocate aliasing registers to interfering live intervals.
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// All other elements (non-aliasing combinations) will have zero cost. Note
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// that the spill option (element 0,0) has zero cost, since we can allocate
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// both intervals to memory safely (the cost for each individual allocation
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// to memory is accounted for by the cost vectors for each live interval).
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PBQP::Matrix *m =
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new PBQP::Matrix(allowed1.size() + 1, allowed2.size() + 1, 0);
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// Assume this is a zero matrix until proven otherwise. Zero matrices occur
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// between interfering live ranges with non-overlapping register sets (e.g.
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// non-overlapping reg classes, or disjoint sets of allowed regs within the
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// same class). The term "overlapping" is used advisedly: sets which do not
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// intersect, but contain registers which alias, will have non-zero matrices.
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// We optimize zero matrices away to improve solver speed.
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bool isZeroMatrix = true;
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// Row index. Starts at 1, since the 0th row is for the spill option, which
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// is always zero.
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unsigned ri = 1;
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// Iterate over allowed sets, insert infinities where required.
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for (RegContainerIterator a1Itr = allowed1.begin(), a1End = allowed1.end();
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a1Itr != a1End; ++a1Itr) {
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// Column index, starts at 1 as for row index.
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unsigned ci = 1;
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unsigned reg1 = *a1Itr;
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for (RegContainerIterator a2Itr = allowed2.begin(), a2End = allowed2.end();
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a2Itr != a2End; ++a2Itr) {
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unsigned reg2 = *a2Itr;
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// If the row/column regs are identical or alias insert an infinity.
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if (tri->regsOverlap(reg1, reg2)) {
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(*m)[ri][ci] = std::numeric_limits<PBQP::PBQPNum>::infinity();
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isZeroMatrix = false;
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}
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++ci;
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}
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++ri;
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}
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// If this turns out to be a zero matrix...
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if (isZeroMatrix) {
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// free it and return null.
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delete m;
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return 0;
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}
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// ...otherwise return the cost matrix.
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return m;
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}
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template <typename RegContainer>
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PBQP::Matrix* RegAllocPBQP::buildCoalescingMatrix(
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const RegContainer &allowed1, const RegContainer &allowed2,
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PBQP::PBQPNum cBenefit) const {
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typedef typename RegContainer::const_iterator RegContainerIterator;
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// Construct a PBQP Matrix representing the benefits of coalescing. As with
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// interference matrices the rows and columns represent allowed registers
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// for the LiveIntervals which are (potentially) to be coalesced. The amount
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// -cBenefit will be placed in any element representing the same register
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// for both intervals.
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PBQP::Matrix *m =
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new PBQP::Matrix(allowed1.size() + 1, allowed2.size() + 1, 0);
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// Reset costs to zero.
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m->reset(0);
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// Assume the matrix is zero till proven otherwise. Zero matrices will be
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// optimized away as in the interference case.
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bool isZeroMatrix = true;
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// Row index. Starts at 1, since the 0th row is for the spill option, which
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// is always zero.
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unsigned ri = 1;
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// Iterate over the allowed sets, insert coalescing benefits where
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// appropriate.
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for (RegContainerIterator a1Itr = allowed1.begin(), a1End = allowed1.end();
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a1Itr != a1End; ++a1Itr) {
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// Column index, starts at 1 as for row index.
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unsigned ci = 1;
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unsigned reg1 = *a1Itr;
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for (RegContainerIterator a2Itr = allowed2.begin(), a2End = allowed2.end();
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a2Itr != a2End; ++a2Itr) {
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// If the row and column represent the same register insert a beneficial
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// cost to preference this allocation - it would allow us to eliminate a
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// move instruction.
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if (reg1 == *a2Itr) {
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(*m)[ri][ci] = -cBenefit;
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isZeroMatrix = false;
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}
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++ci;
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}
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++ri;
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}
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// If this turns out to be a zero matrix...
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if (isZeroMatrix) {
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// ...free it and return null.
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delete m;
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return 0;
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}
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return m;
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}
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RegAllocPBQP::CoalesceMap RegAllocPBQP::findCoalesces() {
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typedef MachineFunction::const_iterator MFIterator;
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typedef MachineBasicBlock::const_iterator MBBIterator;
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typedef LiveInterval::const_vni_iterator VNIIterator;
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CoalesceMap coalescesFound;
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// To find coalesces we need to iterate over the function looking for
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// copy instructions.
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for (MFIterator bbItr = mf->begin(), bbEnd = mf->end();
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bbItr != bbEnd; ++bbItr) {
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const MachineBasicBlock *mbb = &*bbItr;
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for (MBBIterator iItr = mbb->begin(), iEnd = mbb->end();
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iItr != iEnd; ++iItr) {
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const MachineInstr *instr = &*iItr;
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// If this isn't a copy then continue to the next instruction.
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if (!instr->isCopy())
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continue;
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unsigned srcReg = instr->getOperand(1).getReg();
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unsigned dstReg = instr->getOperand(0).getReg();
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// If the registers are already the same our job is nice and easy.
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if (dstReg == srcReg)
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continue;
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bool srcRegIsPhysical = TargetRegisterInfo::isPhysicalRegister(srcReg),
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dstRegIsPhysical = TargetRegisterInfo::isPhysicalRegister(dstReg);
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// If both registers are physical then we can't coalesce.
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if (srcRegIsPhysical && dstRegIsPhysical)
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continue;
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// If it's a copy that includes two virtual register but the source and
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// destination classes differ then we can't coalesce.
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if (!srcRegIsPhysical && !dstRegIsPhysical &&
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mri->getRegClass(srcReg) != mri->getRegClass(dstReg))
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continue;
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// If one is physical and one is virtual, check that the physical is
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// allocatable in the class of the virtual.
|
|
if (srcRegIsPhysical && !dstRegIsPhysical) {
|
|
const TargetRegisterClass *dstRegClass = mri->getRegClass(dstReg);
|
|
if (std::find(dstRegClass->allocation_order_begin(*mf),
|
|
dstRegClass->allocation_order_end(*mf), srcReg) ==
|
|
dstRegClass->allocation_order_end(*mf))
|
|
continue;
|
|
}
|
|
if (!srcRegIsPhysical && dstRegIsPhysical) {
|
|
const TargetRegisterClass *srcRegClass = mri->getRegClass(srcReg);
|
|
if (std::find(srcRegClass->allocation_order_begin(*mf),
|
|
srcRegClass->allocation_order_end(*mf), dstReg) ==
|
|
srcRegClass->allocation_order_end(*mf))
|
|
continue;
|
|
}
|
|
|
|
// If we've made it here we have a copy with compatible register classes.
|
|
// We can probably coalesce, but we need to consider overlap.
|
|
const LiveInterval *srcLI = &lis->getInterval(srcReg),
|
|
*dstLI = &lis->getInterval(dstReg);
|
|
|
|
if (srcLI->overlaps(*dstLI)) {
|
|
// Even in the case of an overlap we might still be able to coalesce,
|
|
// but we need to make sure that no definition of either range occurs
|
|
// while the other range is live.
|
|
|
|
// Otherwise start by assuming we're ok.
|
|
bool badDef = false;
|
|
|
|
// Test all defs of the source range.
|
|
for (VNIIterator
|
|
vniItr = srcLI->vni_begin(), vniEnd = srcLI->vni_end();
|
|
vniItr != vniEnd; ++vniItr) {
|
|
|
|
// If we find a poorly defined def we err on the side of caution.
|
|
if (!(*vniItr)->def.isValid()) {
|
|
badDef = true;
|
|
break;
|
|
}
|
|
|
|
// If we find a def that kills the coalescing opportunity then
|
|
// record it and break from the loop.
|
|
if (dstLI->liveAt((*vniItr)->def)) {
|
|
badDef = true;
|
|
break;
|
|
}
|
|
}
|
|
|
|
// If we have a bad def give up, continue to the next instruction.
|
|
if (badDef)
|
|
continue;
|
|
|
|
// Otherwise test definitions of the destination range.
|
|
for (VNIIterator
|
|
vniItr = dstLI->vni_begin(), vniEnd = dstLI->vni_end();
|
|
vniItr != vniEnd; ++vniItr) {
|
|
|
|
// We want to make sure we skip the copy instruction itself.
|
|
if ((*vniItr)->getCopy() == instr)
|
|
continue;
|
|
|
|
if (!(*vniItr)->def.isValid()) {
|
|
badDef = true;
|
|
break;
|
|
}
|
|
|
|
if (srcLI->liveAt((*vniItr)->def)) {
|
|
badDef = true;
|
|
break;
|
|
}
|
|
}
|
|
|
|
// As before a bad def we give up and continue to the next instr.
|
|
if (badDef)
|
|
continue;
|
|
}
|
|
|
|
// If we make it to here then either the ranges didn't overlap, or they
|
|
// did, but none of their definitions would prevent us from coalescing.
|
|
// We're good to go with the coalesce.
|
|
|
|
float cBenefit = std::pow(10.0f, (float)loopInfo->getLoopDepth(mbb)) / 5.0;
|
|
|
|
coalescesFound[RegPair(srcReg, dstReg)] = cBenefit;
|
|
coalescesFound[RegPair(dstReg, srcReg)] = cBenefit;
|
|
}
|
|
|
|
}
|
|
|
|
return coalescesFound;
|
|
}
|
|
|
|
void RegAllocPBQP::findVRegIntervalsToAlloc() {
|
|
|
|
// Iterate over all live ranges.
|
|
for (LiveIntervals::iterator itr = lis->begin(), end = lis->end();
|
|
itr != end; ++itr) {
|
|
|
|
// Ignore physical ones.
|
|
if (TargetRegisterInfo::isPhysicalRegister(itr->first))
|
|
continue;
|
|
|
|
LiveInterval *li = itr->second;
|
|
|
|
// If this live interval is non-empty we will use pbqp to allocate it.
|
|
// Empty intervals we allocate in a simple post-processing stage in
|
|
// finalizeAlloc.
|
|
if (!li->empty()) {
|
|
vregsToAlloc.insert(li->reg);
|
|
}
|
|
else {
|
|
emptyIntervalVRegs.insert(li->reg);
|
|
}
|
|
}
|
|
}
|
|
|
|
PBQP::Graph RegAllocPBQP::constructPBQPProblem() {
|
|
|
|
typedef std::vector<const LiveInterval*> LIVector;
|
|
typedef std::vector<unsigned> RegVector;
|
|
|
|
// This will store the physical intervals for easy reference.
|
|
LIVector physIntervals;
|
|
|
|
// Start by clearing the old node <-> live interval mappings & allowed sets
|
|
li2Node.clear();
|
|
node2LI.clear();
|
|
allowedSets.clear();
|
|
|
|
// Populate physIntervals, update preg use:
|
|
for (LiveIntervals::iterator itr = lis->begin(), end = lis->end();
|
|
itr != end; ++itr) {
|
|
|
|
if (TargetRegisterInfo::isPhysicalRegister(itr->first)) {
|
|
physIntervals.push_back(itr->second);
|
|
mri->setPhysRegUsed(itr->second->reg);
|
|
}
|
|
}
|
|
|
|
// Iterate over vreg intervals, construct live interval <-> node number
|
|
// mappings.
|
|
for (RegSet::const_iterator itr = vregsToAlloc.begin(),
|
|
end = vregsToAlloc.end();
|
|
itr != end; ++itr) {
|
|
const LiveInterval *li = &lis->getInterval(*itr);
|
|
|
|
li2Node[li] = node2LI.size();
|
|
node2LI.push_back(li);
|
|
}
|
|
|
|
// Get the set of potential coalesces.
|
|
CoalesceMap coalesces;
|
|
|
|
if (pbqpCoalescing) {
|
|
coalesces = findCoalesces();
|
|
}
|
|
|
|
// Construct a PBQP solver for this problem
|
|
PBQP::Graph problem;
|
|
problemNodes.resize(vregsToAlloc.size());
|
|
|
|
// Resize allowedSets container appropriately.
|
|
allowedSets.resize(vregsToAlloc.size());
|
|
|
|
BitVector ReservedRegs = tri->getReservedRegs(*mf);
|
|
|
|
// Iterate over virtual register intervals to compute allowed sets...
|
|
for (unsigned node = 0; node < node2LI.size(); ++node) {
|
|
|
|
// Grab pointers to the interval and its register class.
|
|
const LiveInterval *li = node2LI[node];
|
|
const TargetRegisterClass *liRC = mri->getRegClass(li->reg);
|
|
|
|
// Start by assuming all allocable registers in the class are allowed...
|
|
RegVector liAllowed;
|
|
TargetRegisterClass::iterator aob = liRC->allocation_order_begin(*mf);
|
|
TargetRegisterClass::iterator aoe = liRC->allocation_order_end(*mf);
|
|
for (TargetRegisterClass::iterator it = aob; it != aoe; ++it)
|
|
if (!ReservedRegs.test(*it))
|
|
liAllowed.push_back(*it);
|
|
|
|
// Eliminate the physical registers which overlap with this range, along
|
|
// with all their aliases.
|
|
for (LIVector::iterator pItr = physIntervals.begin(),
|
|
pEnd = physIntervals.end(); pItr != pEnd; ++pItr) {
|
|
|
|
if (!li->overlaps(**pItr))
|
|
continue;
|
|
|
|
unsigned pReg = (*pItr)->reg;
|
|
|
|
// If we get here then the live intervals overlap, but we're still ok
|
|
// if they're coalescable.
|
|
if (coalesces.find(RegPair(li->reg, pReg)) != coalesces.end()) {
|
|
DEBUG(dbgs() << "CoalescingOverride: (" << li->reg << ", " << pReg << ")\n");
|
|
continue;
|
|
}
|
|
|
|
// If we get here then we have a genuine exclusion.
|
|
|
|
// Remove the overlapping reg...
|
|
RegVector::iterator eraseItr =
|
|
std::find(liAllowed.begin(), liAllowed.end(), pReg);
|
|
|
|
if (eraseItr != liAllowed.end())
|
|
liAllowed.erase(eraseItr);
|
|
|
|
const unsigned *aliasItr = tri->getAliasSet(pReg);
|
|
|
|
if (aliasItr != 0) {
|
|
// ...and its aliases.
|
|
for (; *aliasItr != 0; ++aliasItr) {
|
|
RegVector::iterator eraseItr =
|
|
std::find(liAllowed.begin(), liAllowed.end(), *aliasItr);
|
|
|
|
if (eraseItr != liAllowed.end()) {
|
|
liAllowed.erase(eraseItr);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
// Copy the allowed set into a member vector for use when constructing cost
|
|
// vectors & matrices, and mapping PBQP solutions back to assignments.
|
|
allowedSets[node] = AllowedSet(liAllowed.begin(), liAllowed.end());
|
|
|
|
// Set the spill cost to the interval weight, or epsilon if the
|
|
// interval weight is zero
|
|
PBQP::PBQPNum spillCost = (li->weight != 0.0) ?
|
|
li->weight : std::numeric_limits<PBQP::PBQPNum>::min();
|
|
|
|
// Build a cost vector for this interval.
|
|
problemNodes[node] =
|
|
problem.addNode(
|
|
buildCostVector(li->reg, allowedSets[node], coalesces, spillCost));
|
|
|
|
}
|
|
|
|
|
|
// Now add the cost matrices...
|
|
for (unsigned node1 = 0; node1 < node2LI.size(); ++node1) {
|
|
const LiveInterval *li = node2LI[node1];
|
|
|
|
// Test for live range overlaps and insert interference matrices.
|
|
for (unsigned node2 = node1 + 1; node2 < node2LI.size(); ++node2) {
|
|
const LiveInterval *li2 = node2LI[node2];
|
|
|
|
CoalesceMap::const_iterator cmItr =
|
|
coalesces.find(RegPair(li->reg, li2->reg));
|
|
|
|
PBQP::Matrix *m = 0;
|
|
|
|
if (cmItr != coalesces.end()) {
|
|
m = buildCoalescingMatrix(allowedSets[node1], allowedSets[node2],
|
|
cmItr->second);
|
|
}
|
|
else if (li->overlaps(*li2)) {
|
|
m = buildInterferenceMatrix(allowedSets[node1], allowedSets[node2]);
|
|
}
|
|
|
|
if (m != 0) {
|
|
problem.addEdge(problemNodes[node1],
|
|
problemNodes[node2],
|
|
*m);
|
|
|
|
delete m;
|
|
}
|
|
}
|
|
}
|
|
|
|
assert(problem.getNumNodes() == allowedSets.size());
|
|
/*
|
|
std::cerr << "Allocating for " << problem.getNumNodes() << " nodes, "
|
|
<< problem.getNumEdges() << " edges.\n";
|
|
|
|
problem.printDot(std::cerr);
|
|
*/
|
|
// We're done, PBQP problem constructed - return it.
|
|
return problem;
|
|
}
|
|
|
|
void RegAllocPBQP::addStackInterval(const LiveInterval *spilled,
|
|
MachineRegisterInfo* mri) {
|
|
int stackSlot = vrm->getStackSlot(spilled->reg);
|
|
|
|
if (stackSlot == VirtRegMap::NO_STACK_SLOT)
|
|
return;
|
|
|
|
const TargetRegisterClass *RC = mri->getRegClass(spilled->reg);
|
|
LiveInterval &stackInterval = lss->getOrCreateInterval(stackSlot, RC);
|
|
|
|
VNInfo *vni;
|
|
if (stackInterval.getNumValNums() != 0)
|
|
vni = stackInterval.getValNumInfo(0);
|
|
else
|
|
vni = stackInterval.getNextValue(
|
|
SlotIndex(), 0, false, lss->getVNInfoAllocator());
|
|
|
|
LiveInterval &rhsInterval = lis->getInterval(spilled->reg);
|
|
stackInterval.MergeRangesInAsValue(rhsInterval, vni);
|
|
}
|
|
|
|
bool RegAllocPBQP::mapPBQPToRegAlloc(const PBQP::Solution &solution) {
|
|
|
|
// Set to true if we have any spills
|
|
bool anotherRoundNeeded = false;
|
|
|
|
// Clear the existing allocation.
|
|
vrm->clearAllVirt();
|
|
|
|
// Iterate over the nodes mapping the PBQP solution to a register assignment.
|
|
for (unsigned node = 0; node < node2LI.size(); ++node) {
|
|
unsigned virtReg = node2LI[node]->reg,
|
|
allocSelection = solution.getSelection(problemNodes[node]);
|
|
|
|
|
|
// If the PBQP solution is non-zero it's a physical register...
|
|
if (allocSelection != 0) {
|
|
// Get the physical reg, subtracting 1 to account for the spill option.
|
|
unsigned physReg = allowedSets[node][allocSelection - 1];
|
|
|
|
DEBUG(dbgs() << "VREG " << virtReg << " -> "
|
|
<< tri->getName(physReg) << " (Option: " << allocSelection << ")\n");
|
|
|
|
assert(physReg != 0);
|
|
|
|
// Add to the virt reg map and update the used phys regs.
|
|
vrm->assignVirt2Phys(virtReg, physReg);
|
|
}
|
|
// ...Otherwise it's a spill.
|
|
else {
|
|
|
|
// Make sure we ignore this virtual reg on the next round
|
|
// of allocation
|
|
vregsToAlloc.erase(virtReg);
|
|
|
|
// Insert spill ranges for this live range
|
|
const LiveInterval *spillInterval = node2LI[node];
|
|
double oldSpillWeight = spillInterval->weight;
|
|
SmallVector<LiveInterval*, 8> spillIs;
|
|
rmf->rememberUseDefs(spillInterval);
|
|
std::vector<LiveInterval*> newSpills =
|
|
lis->addIntervalsForSpills(*spillInterval, spillIs, loopInfo, *vrm);
|
|
addStackInterval(spillInterval, mri);
|
|
rmf->rememberSpills(spillInterval, newSpills);
|
|
|
|
(void) oldSpillWeight;
|
|
DEBUG(dbgs() << "VREG " << virtReg << " -> SPILLED (Option: 0, Cost: "
|
|
<< oldSpillWeight << ", New vregs: ");
|
|
|
|
// Copy any newly inserted live intervals into the list of regs to
|
|
// allocate.
|
|
for (std::vector<LiveInterval*>::const_iterator
|
|
itr = newSpills.begin(), end = newSpills.end();
|
|
itr != end; ++itr) {
|
|
|
|
assert(!(*itr)->empty() && "Empty spill range.");
|
|
|
|
DEBUG(dbgs() << (*itr)->reg << " ");
|
|
|
|
vregsToAlloc.insert((*itr)->reg);
|
|
}
|
|
|
|
DEBUG(dbgs() << ")\n");
|
|
|
|
// We need another round if spill intervals were added.
|
|
anotherRoundNeeded |= !newSpills.empty();
|
|
}
|
|
}
|
|
|
|
return !anotherRoundNeeded;
|
|
}
|
|
|
|
bool RegAllocPBQP::mapPBQPToRegAlloc2(const PBQPRAProblem &problem,
|
|
const PBQP::Solution &solution) {
|
|
// Set to true if we have any spills
|
|
bool anotherRoundNeeded = false;
|
|
|
|
// Clear the existing allocation.
|
|
vrm->clearAllVirt();
|
|
|
|
const PBQP::Graph &g = problem.getGraph();
|
|
// Iterate over the nodes mapping the PBQP solution to a register
|
|
// assignment.
|
|
for (PBQP::Graph::ConstNodeItr node = g.nodesBegin(),
|
|
nodeEnd = g.nodesEnd();
|
|
node != nodeEnd; ++node) {
|
|
unsigned vreg = problem.getVRegForNode(node);
|
|
unsigned alloc = solution.getSelection(node);
|
|
|
|
if (problem.isPRegOption(vreg, alloc)) {
|
|
unsigned preg = problem.getPRegForOption(vreg, alloc);
|
|
DEBUG(dbgs() << "VREG " << vreg << " -> " << tri->getName(preg) << "\n");
|
|
assert(preg != 0 && "Invalid preg selected.");
|
|
vrm->assignVirt2Phys(vreg, preg);
|
|
} else if (problem.isSpillOption(vreg, alloc)) {
|
|
vregsToAlloc.erase(vreg);
|
|
const LiveInterval* spillInterval = &lis->getInterval(vreg);
|
|
double oldWeight = spillInterval->weight;
|
|
SmallVector<LiveInterval*, 8> spillIs;
|
|
rmf->rememberUseDefs(spillInterval);
|
|
std::vector<LiveInterval*> newSpills =
|
|
lis->addIntervalsForSpills(*spillInterval, spillIs, loopInfo, *vrm);
|
|
addStackInterval(spillInterval, mri);
|
|
rmf->rememberSpills(spillInterval, newSpills);
|
|
|
|
(void) oldWeight;
|
|
DEBUG(dbgs() << "VREG " << vreg << " -> SPILLED (Cost: "
|
|
<< oldWeight << ", New vregs: ");
|
|
|
|
// Copy any newly inserted live intervals into the list of regs to
|
|
// allocate.
|
|
for (std::vector<LiveInterval*>::const_iterator
|
|
itr = newSpills.begin(), end = newSpills.end();
|
|
itr != end; ++itr) {
|
|
assert(!(*itr)->empty() && "Empty spill range.");
|
|
DEBUG(dbgs() << (*itr)->reg << " ");
|
|
vregsToAlloc.insert((*itr)->reg);
|
|
}
|
|
|
|
DEBUG(dbgs() << ")\n");
|
|
|
|
// We need another round if spill intervals were added.
|
|
anotherRoundNeeded |= !newSpills.empty();
|
|
} else {
|
|
assert(false && "Unknown allocation option.");
|
|
}
|
|
}
|
|
|
|
return !anotherRoundNeeded;
|
|
}
|
|
|
|
|
|
void RegAllocPBQP::finalizeAlloc() const {
|
|
typedef LiveIntervals::iterator LIIterator;
|
|
typedef LiveInterval::Ranges::const_iterator LRIterator;
|
|
|
|
// First allocate registers for the empty intervals.
|
|
for (RegSet::const_iterator
|
|
itr = emptyIntervalVRegs.begin(), end = emptyIntervalVRegs.end();
|
|
itr != end; ++itr) {
|
|
LiveInterval *li = &lis->getInterval(*itr);
|
|
|
|
unsigned physReg = vrm->getRegAllocPref(li->reg);
|
|
|
|
if (physReg == 0) {
|
|
const TargetRegisterClass *liRC = mri->getRegClass(li->reg);
|
|
physReg = *liRC->allocation_order_begin(*mf);
|
|
}
|
|
|
|
vrm->assignVirt2Phys(li->reg, physReg);
|
|
}
|
|
|
|
// Finally iterate over the basic blocks to compute and set the live-in sets.
|
|
SmallVector<MachineBasicBlock*, 8> liveInMBBs;
|
|
MachineBasicBlock *entryMBB = &*mf->begin();
|
|
|
|
for (LIIterator liItr = lis->begin(), liEnd = lis->end();
|
|
liItr != liEnd; ++liItr) {
|
|
|
|
const LiveInterval *li = liItr->second;
|
|
unsigned reg = 0;
|
|
|
|
// Get the physical register for this interval
|
|
if (TargetRegisterInfo::isPhysicalRegister(li->reg)) {
|
|
reg = li->reg;
|
|
}
|
|
else if (vrm->isAssignedReg(li->reg)) {
|
|
reg = vrm->getPhys(li->reg);
|
|
}
|
|
else {
|
|
// Ranges which are assigned a stack slot only are ignored.
|
|
continue;
|
|
}
|
|
|
|
if (reg == 0) {
|
|
// Filter out zero regs - they're for intervals that were spilled.
|
|
continue;
|
|
}
|
|
|
|
// Iterate over the ranges of the current interval...
|
|
for (LRIterator lrItr = li->begin(), lrEnd = li->end();
|
|
lrItr != lrEnd; ++lrItr) {
|
|
|
|
// Find the set of basic blocks which this range is live into...
|
|
if (lis->findLiveInMBBs(lrItr->start, lrItr->end, liveInMBBs)) {
|
|
// And add the physreg for this interval to their live-in sets.
|
|
for (unsigned i = 0; i < liveInMBBs.size(); ++i) {
|
|
if (liveInMBBs[i] != entryMBB) {
|
|
if (!liveInMBBs[i]->isLiveIn(reg)) {
|
|
liveInMBBs[i]->addLiveIn(reg);
|
|
}
|
|
}
|
|
}
|
|
liveInMBBs.clear();
|
|
}
|
|
}
|
|
}
|
|
|
|
}
|
|
|
|
bool RegAllocPBQP::runOnMachineFunction(MachineFunction &MF) {
|
|
|
|
mf = &MF;
|
|
tm = &mf->getTarget();
|
|
tri = tm->getRegisterInfo();
|
|
tii = tm->getInstrInfo();
|
|
mri = &mf->getRegInfo();
|
|
|
|
lis = &getAnalysis<LiveIntervals>();
|
|
lss = &getAnalysis<LiveStacks>();
|
|
loopInfo = &getAnalysis<MachineLoopInfo>();
|
|
rmf = &getAnalysis<RenderMachineFunction>();
|
|
|
|
vrm = &getAnalysis<VirtRegMap>();
|
|
|
|
|
|
DEBUG(dbgs() << "PBQP Register Allocating for " << mf->getFunction()->getName() << "\n");
|
|
|
|
// Allocator main loop:
|
|
//
|
|
// * Map current regalloc problem to a PBQP problem
|
|
// * Solve the PBQP problem
|
|
// * Map the solution back to a register allocation
|
|
// * Spill if necessary
|
|
//
|
|
// This process is continued till no more spills are generated.
|
|
|
|
// Find the vreg intervals in need of allocation.
|
|
findVRegIntervalsToAlloc();
|
|
|
|
// If there are non-empty intervals allocate them using pbqp.
|
|
if (!vregsToAlloc.empty()) {
|
|
|
|
bool pbqpAllocComplete = false;
|
|
unsigned round = 0;
|
|
|
|
if (!pbqpBuilder) {
|
|
while (!pbqpAllocComplete) {
|
|
DEBUG(dbgs() << " PBQP Regalloc round " << round << ":\n");
|
|
|
|
PBQP::Graph problem = constructPBQPProblem();
|
|
PBQP::Solution solution =
|
|
PBQP::HeuristicSolver<PBQP::Heuristics::Briggs>::solve(problem);
|
|
|
|
pbqpAllocComplete = mapPBQPToRegAlloc(solution);
|
|
|
|
++round;
|
|
}
|
|
} else {
|
|
while (!pbqpAllocComplete) {
|
|
DEBUG(dbgs() << " PBQP Regalloc round " << round << ":\n");
|
|
|
|
std::auto_ptr<PBQPRAProblem> problem =
|
|
builder->build(mf, lis, vregsToAlloc);
|
|
PBQP::Solution solution =
|
|
HeuristicSolver<Briggs>::solve(problem->getGraph());
|
|
|
|
pbqpAllocComplete = mapPBQPToRegAlloc2(*problem, solution);
|
|
|
|
++round;
|
|
}
|
|
}
|
|
}
|
|
|
|
// Finalise allocation, allocate empty ranges.
|
|
finalizeAlloc();
|
|
|
|
rmf->renderMachineFunction("After PBQP register allocation.", vrm);
|
|
|
|
vregsToAlloc.clear();
|
|
emptyIntervalVRegs.clear();
|
|
li2Node.clear();
|
|
node2LI.clear();
|
|
allowedSets.clear();
|
|
problemNodes.clear();
|
|
|
|
DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *vrm << "\n");
|
|
|
|
// Run rewriter
|
|
std::auto_ptr<VirtRegRewriter> rewriter(createVirtRegRewriter());
|
|
|
|
rewriter->runOnMachineFunction(*mf, *vrm, lis);
|
|
|
|
return true;
|
|
}
|
|
|
|
FunctionPass* createPBQPRegisterAllocator() {
|
|
return new RegAllocPBQP(std::auto_ptr<PBQPBuilder>(new PBQPBuilder()));
|
|
}
|
|
|
|
}
|
|
|
|
#undef DEBUG_TYPE
|