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c97d7d26bd
ARM targets with NEON units have access to aligned vector loads and stores that are potentially faster than unaligned operations. Add support for spilling the callee-saved NEON registers to an aligned stack area using 16-byte aligned NEON loads and store. This feature is off by default, controlled by an -align-neon-spills command line option. llvm-svn: 147211
96 lines
3.1 KiB
LLVM
96 lines
3.1 KiB
LLVM
; RUN: llc < %s -mcpu=cortex-a8 | FileCheck %s
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; RUN: llc < %s -mcpu=cortex-a8 -align-neon-spills | FileCheck %s --check-prefix=NEON
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target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
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target triple = "thumbv7-apple-ios"
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; CHECK: f
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; This function is forced to spill a double.
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; Verify that the spill slot is properly aligned.
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;
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; The caller-saved r4 is used as a scratch register for stack realignment.
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; CHECK: push {r4, r7, lr}
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; CHECK: bic r4, r4, #7
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; CHECK: mov sp, r4
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define void @f(double* nocapture %p) nounwind ssp {
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entry:
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%0 = load double* %p, align 4
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tail call void asm sideeffect "", "~{d8},~{d9},~{d10},~{d11},~{d12},~{d13},~{d14},~{d15}"() nounwind
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tail call void @g() nounwind
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store double %0, double* %p, align 4
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ret void
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}
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; NEON: f
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; NEON: push {r4, r7, lr}
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; NEON: sub.w r4, sp, #64
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; NEON: bic r4, r4, #15
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; Stack pointer must be updated before the spills.
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; NEON: mov sp, r4
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; NEON: vst1.64 {d8, d9, d10, d11}, [r4, :128]!
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; NEON: vst1.64 {d12, d13, d14, d15}, [r4, :128]
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; Stack pointer adjustment for the stack frame contents.
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; This could legally happen before the spills.
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; Since the spill slot is only 8 bytes, technically it would be fine to only
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; subtract #8 here. That would leave sp less aligned than some stack slots,
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; and would probably blow MFI's mind.
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; NEON: sub sp, #16
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; The epilog is free to use another scratch register than r4.
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; NEON: add r[[R4:[0-9]+]], sp, #16
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; NEON: vld1.64 {d8, d9, d10, d11}, [r[[R4]], :128]!
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; NEON: vld1.64 {d12, d13, d14, d15}, [r[[R4]], :128]
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; The stack pointer restore must happen after the reloads.
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; NEON: mov sp,
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; NEON: pop
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declare void @g()
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; Spill 7 d-registers.
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define void @f7(double* nocapture %p) nounwind ssp {
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entry:
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tail call void asm sideeffect "", "~{d8},~{d9},~{d10},~{d11},~{d12},~{d13},~{d14}"() nounwind
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ret void
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}
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; NEON: f7
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; NEON: push {r4, r7, lr}
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; NEON: sub.w r4, sp, #56
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; NEON: bic r4, r4, #15
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; Stack pointer must be updated before the spills.
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; NEON: mov sp, r4
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; NEON: vst1.64 {d8, d9, d10, d11}, [r4, :128]!
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; NEON: vst1.64 {d12, d13}, [r4, :128]
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; NEON: vstr d14, [r4, #16]
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; Epilog
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; NEON: vld1.64 {d8, d9, d10, d11},
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; NEON: vld1.64 {d12, d13},
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; NEON: vldr d14,
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; The stack pointer restore must happen after the reloads.
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; NEON: mov sp,
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; NEON: pop
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; Spill 7 d-registers, leave a hole.
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define void @f3plus4(double* nocapture %p) nounwind ssp {
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entry:
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tail call void asm sideeffect "", "~{d8},~{d9},~{d10},~{d12},~{d13},~{d14},~{d15}"() nounwind
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ret void
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}
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; Aligned spilling only works for contiguous ranges starting from d8.
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; The rest goes to the standard vpush instructions.
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; NEON: f3plus4
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; NEON: push {r4, r7, lr}
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; NEON: vpush {d12, d13, d14, d15}
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; NEON: sub.w r4, sp, #24
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; NEON: bic r4, r4, #15
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; Stack pointer must be updated before the spills.
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; NEON: mov sp, r4
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; NEON: vst1.64 {d8, d9}, [r4, :128]
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; NEON: vstr d10, [r4, #16]
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; Epilog
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; NEON: vld1.64 {d8, d9},
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; NEON: vldr d10, [{{.*}}, #16]
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; The stack pointer restore must happen after the reloads.
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; NEON: mov sp,
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; NEON: vpop {d12, d13, d14, d15}
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; NEON: pop
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