Sander de Smalen 332291dd3b [TableGen][AsmMatcherEmitter] Only choose specific diagnostic for enabled instruction ...

Summary:
When emitting a diagnostic for an invalid operand, a specific diagnostic
should only be reported when the instruction being matched is actually
enabled by the feature flags.

Patch [3/4] in a series to add parsing of predicates and properly parse SVE 
ZIP1/ZIP2 instructions. This patch fixes bogus diagnostic messages for when
the SVE feature is not specified.

Reviewers: rengolin, craig.topper, olista01, sdardis, stoklund

Reviewed By: olista01, sdardis

Subscribers: fhahn, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D40362

llvm-svn: 320986

2017-12-18 14:34:24 +00:00

..

AArch64

[TableGen][AsmMatcherEmitter] Only choose specific diagnostic for enabled instruction

2017-12-18 14:34:24 +00:00

AMDGPU

[AMDGPU][MC][GFX9] Corrected encoding of ttmp registers, disabled tba/tma

2017-12-11 15:23:20 +00:00

ARM

[DWARFv5] Emit v5 line table header.

2017-12-05 20:35:00 +00:00

AsmParser

[CodeGen] Unify MBB reference format in both MIR and debug output

2017-12-04 17:18:51 +00:00

AVR

[AVR] Implement some missing code paths

2017-12-11 11:01:27 +00:00

BPF

bpf: print backward branch target properly

2017-11-16 19:15:36 +00:00

COFF

[CodeGen] Unify MBB reference format in both MIR and debug output

2017-12-04 17:18:51 +00:00

Disassembler

AMDGPU: Partially fix disassembly of MIMG instructions

2017-12-13 21:07:51 +00:00

ELF

Re-submit r289925 (Update .debug_line section version to match DWARF version)

2017-12-04 21:27:46 +00:00

Hexagon

[Hexagon] Add support for Hexagon V65

2017-12-11 18:57:54 +00:00

Lanai

[lanai] Add more tests for assembly of conditional ALU ops

2016-07-11 17:58:16 +00:00

MachO

[MC] Allow .file directives to be out-of-order

2017-12-14 18:46:43 +00:00

Markup

…

Mips

[TableGen][AsmMatcherEmitter] Only choose specific diagnostic for enabled instruction

2017-12-18 14:34:24 +00:00

PowerPC

[PowerPC, AsmParser] Enable the mnemonic spell corrector

2017-12-16 02:42:18 +00:00

RISCV

[RISCV] Change shift amount operand of RVC shift instructions to uimmlog2xlennonzero

2017-12-15 10:20:51 +00:00

Sparc

[Sparc] invalid adjustments in TLS_LE/TLS_LDO relocations removed

2017-07-25 15:28:28 +00:00

SystemZ

[SystemZ, AsmParser] Enable the mnemonic spell corrector.

2017-07-18 09:17:00 +00:00

WebAssembly

[WebAssembly] Implement @llvm.global_ctors and @llvm.global_dtors

2017-12-15 00:17:10 +00:00

X86

[X86] Fix XSAVE64 and similar instructions to not be allowed by the assembler in 32-bit mode.

2017-12-15 17:22:58 +00:00