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https://github.com/RPCS3/llvm-mirror.git
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33edb0a6f1
Emitting a schedule is really hard. There are lots of corner cases to take care of; in fact, of the 60+ SWP-specific testcases in the Hexagon backend most of those are testing codegen rather than the schedule creation itself. One issue is that to test an emission corner case we must craft an input such that the generated schedule uses that corner case; sometimes this is very hard and convolutes testcases. Other times it is impossible but we want to test it anyway. This patch adds a simple test pass that will consume a module containing a loop and generate pipelined code from it. We use post-instr-symbols as a way to annotate instructions with the stage and cycle that we want to schedule them at. We also provide a flag that causes the MachinePipeliner to generate these annotations instead of actually emitting code; this allows us to generate an input testcase with: llc < %s -stop-after=pipeliner -pipeliner-annotate-for-testing -o test.mir And run the emission in isolation with: llc < test.mir -run-pass=modulo-schedule-test llvm-svn: 370705
119 lines
4.9 KiB
C++
119 lines
4.9 KiB
C++
//===-- CodeGen.cpp -------------------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the common initialization routines for the
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// CodeGen library.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm-c/Initialization.h"
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#include "llvm/InitializePasses.h"
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#include "llvm/PassRegistry.h"
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using namespace llvm;
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/// initializeCodeGen - Initialize all passes linked into the CodeGen library.
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void llvm::initializeCodeGen(PassRegistry &Registry) {
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initializeAtomicExpandPass(Registry);
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initializeBranchFolderPassPass(Registry);
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initializeBranchRelaxationPass(Registry);
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initializeCFIInstrInserterPass(Registry);
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initializeCodeGenPreparePass(Registry);
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initializeDeadMachineInstructionElimPass(Registry);
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initializeDetectDeadLanesPass(Registry);
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initializeDwarfEHPreparePass(Registry);
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initializeEarlyIfConverterPass(Registry);
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initializeEarlyIfPredicatorPass(Registry);
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initializeEarlyMachineLICMPass(Registry);
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initializeEarlyTailDuplicatePass(Registry);
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initializeExpandMemCmpPassPass(Registry);
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initializeExpandPostRAPass(Registry);
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initializeFEntryInserterPass(Registry);
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initializeFinalizeISelPass(Registry);
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initializeFinalizeMachineBundlesPass(Registry);
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initializeFuncletLayoutPass(Registry);
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initializeGCMachineCodeAnalysisPass(Registry);
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initializeGCModuleInfoPass(Registry);
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initializeHardwareLoopsPass(Registry);
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initializeIfConverterPass(Registry);
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initializeImplicitNullChecksPass(Registry);
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initializeIndirectBrExpandPassPass(Registry);
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initializeInterleavedLoadCombinePass(Registry);
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initializeInterleavedAccessPass(Registry);
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initializeLiveDebugValuesPass(Registry);
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initializeLiveDebugVariablesPass(Registry);
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initializeLiveIntervalsPass(Registry);
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initializeLiveRangeShrinkPass(Registry);
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initializeLiveStacksPass(Registry);
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initializeLiveVariablesPass(Registry);
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initializeLocalStackSlotPassPass(Registry);
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initializeLowerIntrinsicsPass(Registry);
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initializeMIRCanonicalizerPass(Registry);
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initializeMachineBlockFrequencyInfoPass(Registry);
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initializeMachineBlockPlacementPass(Registry);
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initializeMachineBlockPlacementStatsPass(Registry);
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initializeMachineCSEPass(Registry);
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initializeMachineCombinerPass(Registry);
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initializeMachineCopyPropagationPass(Registry);
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initializeMachineDominatorTreePass(Registry);
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initializeMachineFunctionPrinterPassPass(Registry);
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initializeMachineLICMPass(Registry);
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initializeMachineLoopInfoPass(Registry);
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initializeMachineModuleInfoPass(Registry);
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initializeMachineOptimizationRemarkEmitterPassPass(Registry);
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initializeMachineOutlinerPass(Registry);
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initializeMachinePipelinerPass(Registry);
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initializeModuloScheduleTestPass(Registry);
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initializeMachinePostDominatorTreePass(Registry);
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initializeMachineRegionInfoPassPass(Registry);
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initializeMachineSchedulerPass(Registry);
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initializeMachineSinkingPass(Registry);
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initializeMachineVerifierPassPass(Registry);
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initializeOptimizePHIsPass(Registry);
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initializePEIPass(Registry);
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initializePHIEliminationPass(Registry);
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initializePatchableFunctionPass(Registry);
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initializePeepholeOptimizerPass(Registry);
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initializePostMachineSchedulerPass(Registry);
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initializePostRAHazardRecognizerPass(Registry);
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initializePostRAMachineSinkingPass(Registry);
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initializePostRASchedulerPass(Registry);
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initializePreISelIntrinsicLoweringLegacyPassPass(Registry);
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initializeProcessImplicitDefsPass(Registry);
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initializeRABasicPass(Registry);
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initializeRAGreedyPass(Registry);
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initializeRegAllocFastPass(Registry);
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initializeRegUsageInfoCollectorPass(Registry);
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initializeRegUsageInfoPropagationPass(Registry);
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initializeRegisterCoalescerPass(Registry);
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initializeRenameIndependentSubregsPass(Registry);
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initializeSafeStackLegacyPassPass(Registry);
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initializeScalarizeMaskedMemIntrinPass(Registry);
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initializeShrinkWrapPass(Registry);
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initializeSlotIndexesPass(Registry);
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initializeStackColoringPass(Registry);
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initializeStackMapLivenessPass(Registry);
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initializeStackProtectorPass(Registry);
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initializeStackSlotColoringPass(Registry);
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initializeTailDuplicatePass(Registry);
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initializeTargetPassConfigPass(Registry);
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initializeTwoAddressInstructionPassPass(Registry);
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initializeUnpackMachineBundlesPass(Registry);
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initializeUnreachableBlockElimLegacyPassPass(Registry);
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initializeUnreachableMachineBlockElimPass(Registry);
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initializeVirtRegMapPass(Registry);
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initializeVirtRegRewriterPass(Registry);
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initializeWasmEHPreparePass(Registry);
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initializeWinEHPreparePass(Registry);
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initializeXRayInstrumentationPass(Registry);
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}
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void LLVMInitializeCodeGen(LLVMPassRegistryRef R) {
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initializeCodeGen(*unwrap(R));
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}
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