Kai Nacke 59a31f2f53 [mips] Add new format for dmtc2/dmfc2 for Octeon CPUs. ...

Octeon CPUs use dmtc2 rt,imm16 and dmfcp2 rt,imm16 for the crypto coprocessor.
E.g. dmtc2 rt,0x4057 starts calculation of sha-1.

I had to introduce a new deconding namespace to avoid a decoding conflict.

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D10083

llvm-svn: 238439

2015-05-28 16:23:16 +00:00

..

AArch64

[AArch64] Clean up the ELF streamer a bit.

2015-05-23 16:39:10 +00:00

ARM

ARMTargetParser: Normalising build attributes

2015-05-27 18:15:37 +00:00

AsmParser

Relax these tests a bit.

2015-05-22 21:37:13 +00:00

COFF

Don't omit the constant when computing a cross-section relative relocation.

2015-05-14 01:10:41 +00:00

Disassembler

[mips][microMIPSr6] Implement SEB and SEH instructions

2015-05-27 15:39:47 +00:00

ELF

Don't create an unused _GLOBAL_OFFSET_TABLE_.

2015-05-28 15:20:00 +00:00

Hexagon

Expand MUX instructions early on Hexagon

2015-03-31 13:35:12 +00:00

MachO

AArch64: work around ld64 bug more aggressively.

2015-05-18 22:07:20 +00:00

Markup

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Mips

[mips] Add new format for dmtc2/dmfc2 for Octeon CPUs.

2015-05-28 16:23:16 +00:00

PowerPC

This patch adds support for the vector quadword add/sub instructions introduced

2015-05-25 15:49:26 +00:00

R600

R600/SI: Add assembler support for all CI and VI VOP2 instructions

2015-05-26 15:55:52 +00:00

Sparc

Sparc: support the "set" synthetic instruction.

2015-05-18 16:43:33 +00:00

SystemZ

[SystemZ] Add z13 vector facility and MC support

2015-05-05 19:23:40 +00:00

X86

AVX-512: Implemented all forms of sign-extend and zero-extend instructions for KNL and SKX

2015-05-27 08:15:19 +00:00