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284e8e1c63
Currently shufflemasks get emitted as any other constant, and you end up with a bunch of virtual registers of G_CONSTANT with a G_BUILD_VECTOR. The AArch64 selector then asserts on anything that doesn't fit this pattern. This isn't an ideal representation, and should avoid legalization and have fewer opportunities for a representational error. Rather than invent a new shuffle mask operand type, similar to what ShuffleVectorSDNode does, just track the original IR Constant mask operand. I don't completely like the idea of adding another link to the IR, but MIR is already quite dependent on IR constants already, and this will allow sharing the shuffle mask utility functions with the IR. llvm-svn: 368704
20 lines
492 B
YAML
20 lines
492 B
YAML
# RUN: not llc -mtriple=aarch64-- -run-pass=none -o /dev/null %s 2>&1 | FileCheck %s
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---
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name: test_missing_comma
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0
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%0:_(<2 x s32>) = COPY $d0
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%2:_(<2 x s32>) = G_IMPLICIT_DEF
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; FIXME: Not ideal error
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; CHECK: [[@LINE+1]]:73: shufflemask should be terminated by ')'.
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%1:_(<2 x s32>) = G_SHUFFLE_VECTOR %0(<2 x s32>), %2, shufflemask(1 0)
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$d0 = COPY %1(<2 x s32>)
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RET_ReallyLR implicit $d0
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...
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