llvm-mirror/test/CodeGen/MIR/AArch64/swp.mir
Guillaume Chatelet d49cb60862 [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
Summary:
This catches malformed mir files which specify alignment as log2 instead of pow2.
See https://reviews.llvm.org/D65945 for reference,

This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Reviewers: courbet

Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67433

llvm-svn: 371608
2019-09-11 11:16:48 +00:00

34 lines
838 B
YAML

# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass none -o - %s | FileCheck %s
--- |
define i32 @swp(i32* %addr) #0 {
entry:
%0 = atomicrmw xchg i32* %addr, i32 1 monotonic
ret i32 %0
}
attributes #0 = { "target-features"="+lse" }
...
---
name: swp
alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: gpr64common }
- { id: 1, class: gpr32 }
- { id: 2, class: gpr32 }
liveins:
- { reg: '$x0', virtual-reg: '%0' }
body: |
bb.0.entry:
liveins: $x0
; CHECK-LABEL: swp
; CHECK: {{[0-9]+}}:gpr32 = SWPW killed %1, %0 :: (volatile load store monotonic 4 on %ir.addr)
%0:gpr64common = COPY $x0
%1:gpr32 = MOVi32imm 1
%2:gpr32 = SWPW killed %1, %0 :: (volatile load store monotonic 4 on %ir.addr)
$w0 = COPY %2
RET_ReallyLR implicit $w0
...