mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-12-18 09:09:12 +00:00
dd53274771
This reverts commit 80a34ae31125aa46dcad47162ba45b152aed968d with fixes. Previously, since bots turning on EXPENSIVE_CHECKS are essentially turning on MachineVerifierPass by default on X86 and the fact that inline-asm-avx-v-constraint-32bit.ll and inline-asm-avx512vl-v-constraint-32bit.ll are not expected to generate functioning machine code, this would go down to `report_fatal_error` in MachineVerifierPass. Here passing `-verify-machineinstrs=0` to make the intent explicit.
28 lines
1004 B
TableGen
28 lines
1004 B
TableGen
// RUN: not --crash llvm-tblgen -gen-dag-isel -I %p/../../include %s 2>&1 | FileCheck %s
|
|
|
|
// The HwModeSelect class is intended to serve as a base class for other
|
|
// classes that are then used to select a value based on the HW mode.
|
|
// It contains a list of HW modes, and a derived class should provide a
|
|
// list of corresponding values.
|
|
// These two lists must have the same size. Make sure that a violation of
|
|
// this requirement is diagnosed.
|
|
|
|
include "llvm/Target/Target.td"
|
|
|
|
def TestTargetInstrInfo : InstrInfo;
|
|
|
|
def TestTarget : Target {
|
|
let InstructionSet = TestTargetInstrInfo;
|
|
}
|
|
|
|
def TestReg : Register<"testreg">;
|
|
def TestClass : RegisterClass<"TestTarget", [i32], 32, (add TestReg)>;
|
|
|
|
def TestMode1 : HwMode<"+feat1">;
|
|
def TestMode2 : HwMode<"+feat2">;
|
|
|
|
def BadDef : ValueTypeByHwMode<[TestMode1, TestMode2, DefaultMode],
|
|
[i8, i16, i32, i64]>;
|
|
|
|
// CHECK: error: in record BadDef derived from HwModeSelect: the lists Modes and Objects should have the same size
|