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to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
87 lines
2.1 KiB
C++
87 lines
2.1 KiB
C++
//===-- llvm/CodeGen/MachineCombinerPattern.h - Instruction pattern supported by
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// combiner ------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines instruction pattern supported by combiner
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_MACHINECOMBINERPATTERN_H
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#define LLVM_CODEGEN_MACHINECOMBINERPATTERN_H
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namespace llvm {
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/// These are instruction patterns matched by the machine combiner pass.
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enum class MachineCombinerPattern {
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// These are commutative variants for reassociating a computation chain. See
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// the comments before getMachineCombinerPatterns() in TargetInstrInfo.cpp.
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REASSOC_AX_BY,
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REASSOC_AX_YB,
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REASSOC_XA_BY,
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REASSOC_XA_YB,
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// These are multiply-add patterns matched by the AArch64 machine combiner.
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MULADDW_OP1,
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MULADDW_OP2,
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MULSUBW_OP1,
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MULSUBW_OP2,
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MULADDWI_OP1,
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MULSUBWI_OP1,
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MULADDX_OP1,
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MULADDX_OP2,
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MULSUBX_OP1,
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MULSUBX_OP2,
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MULADDXI_OP1,
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MULSUBXI_OP1,
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// Floating Point
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FMULADDS_OP1,
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FMULADDS_OP2,
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FMULSUBS_OP1,
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FMULSUBS_OP2,
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FMULADDD_OP1,
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FMULADDD_OP2,
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FMULSUBD_OP1,
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FMULSUBD_OP2,
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FNMULSUBS_OP1,
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FNMULSUBD_OP1,
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FMLAv1i32_indexed_OP1,
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FMLAv1i32_indexed_OP2,
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FMLAv1i64_indexed_OP1,
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FMLAv1i64_indexed_OP2,
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FMLAv2f32_OP2,
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FMLAv2f32_OP1,
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FMLAv2f64_OP1,
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FMLAv2f64_OP2,
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FMLAv2i32_indexed_OP1,
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FMLAv2i32_indexed_OP2,
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FMLAv2i64_indexed_OP1,
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FMLAv2i64_indexed_OP2,
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FMLAv4f32_OP1,
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FMLAv4f32_OP2,
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FMLAv4i32_indexed_OP1,
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FMLAv4i32_indexed_OP2,
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FMLSv1i32_indexed_OP2,
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FMLSv1i64_indexed_OP2,
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FMLSv2f32_OP1,
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FMLSv2f32_OP2,
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FMLSv2f64_OP1,
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FMLSv2f64_OP2,
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FMLSv2i32_indexed_OP1,
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FMLSv2i32_indexed_OP2,
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FMLSv2i64_indexed_OP1,
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FMLSv2i64_indexed_OP2,
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FMLSv4f32_OP1,
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FMLSv4f32_OP2,
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FMLSv4i32_indexed_OP1,
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FMLSv4i32_indexed_OP2
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};
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} // end namespace llvm
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#endif
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