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45d6ddee89
As discussed in D11886, this patch moves the SSE/AVX vector blend folding to instcombiner from PerformINTRINSIC_WO_CHAINCombine (which allows us to remove this completely). InstCombiner already had partial support for this, I just had to add support for zero (ConstantAggregateZero) masks and also the case where both selection inputs were the same (allowing us to ignore the mask). I also moved all the relevant combine tests into InstCombine/blend_x86.ll Differential Revision: http://reviews.llvm.org/D11934 llvm-svn: 244723
92 lines
2.7 KiB
LLVM
92 lines
2.7 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=corei7 | FileCheck %s
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define <2 x double> @test_x86_sse41_blend_pd(<2 x double> %a0, <2 x double> %a1) {
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%1 = call <2 x double> @llvm.x86.sse41.blendpd(<2 x double> %a0, <2 x double> %a1, i32 0)
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ret <2 x double> %1
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}
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; CHECK-LABEL: test_x86_sse41_blend_pd
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; CHECK-NOT: blendpd
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; CHECK: ret
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define <4 x float> @test_x86_sse41_blend_ps(<4 x float> %a0, <4 x float> %a1) {
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%1 = call <4 x float> @llvm.x86.sse41.blendps(<4 x float> %a0, <4 x float> %a1, i32 0)
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ret <4 x float> %1
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}
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; CHECK-LABEL: test_x86_sse41_blend_ps
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; CHECK-NOT: blendps
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; CHECK: ret
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define <8 x i16> @test_x86_sse41_pblend_w(<8 x i16> %a0, <8 x i16> %a1) {
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%1 = call <8 x i16> @llvm.x86.sse41.pblendw(<8 x i16> %a0, <8 x i16> %a1, i32 0)
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ret <8 x i16> %1
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}
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; CHECK-LABEL: test_x86_sse41_pblend_w
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; CHECK-NOT: pblendw
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; CHECK: ret
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define <2 x double> @test2_x86_sse41_blend_pd(<2 x double> %a0, <2 x double> %a1) {
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%1 = call <2 x double> @llvm.x86.sse41.blendpd(<2 x double> %a0, <2 x double> %a1, i32 -1)
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ret <2 x double> %1
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}
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; CHECK-LABEL: test2_x86_sse41_blend_pd
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; CHECK-NOT: blendpd
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; CHECK: movaps %xmm1, %xmm0
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; CHECK-NEXT: ret
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define <4 x float> @test2_x86_sse41_blend_ps(<4 x float> %a0, <4 x float> %a1) {
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%1 = call <4 x float> @llvm.x86.sse41.blendps(<4 x float> %a0, <4 x float> %a1, i32 -1)
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ret <4 x float> %1
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}
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; CHECK-LABEL: test2_x86_sse41_blend_ps
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; CHECK-NOT: blendps
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; CHECK: movaps %xmm1, %xmm0
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; CHECK-NEXT: ret
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define <8 x i16> @test2_x86_sse41_pblend_w(<8 x i16> %a0, <8 x i16> %a1) {
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%1 = call <8 x i16> @llvm.x86.sse41.pblendw(<8 x i16> %a0, <8 x i16> %a1, i32 -1)
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ret <8 x i16> %1
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}
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; CHECK-LABEL: test2_x86_sse41_pblend_w
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; CHECK-NOT: pblendw
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; CHECK: movaps %xmm1, %xmm0
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; CHECK-NEXT: ret
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define <2 x double> @test3_x86_sse41_blend_pd(<2 x double> %a0) {
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%1 = call <2 x double> @llvm.x86.sse41.blendpd(<2 x double> %a0, <2 x double> %a0, i32 7)
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ret <2 x double> %1
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}
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; CHECK-LABEL: test3_x86_sse41_blend_pd
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; CHECK-NOT: blendpd
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; CHECK: ret
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define <4 x float> @test3_x86_sse41_blend_ps(<4 x float> %a0) {
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%1 = call <4 x float> @llvm.x86.sse41.blendps(<4 x float> %a0, <4 x float> %a0, i32 7)
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ret <4 x float> %1
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}
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; CHECK-LABEL: test3_x86_sse41_blend_ps
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; CHECK-NOT: blendps
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; CHECK: ret
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define <8 x i16> @test3_x86_sse41_pblend_w(<8 x i16> %a0) {
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%1 = call <8 x i16> @llvm.x86.sse41.pblendw(<8 x i16> %a0, <8 x i16> %a0, i32 7)
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ret <8 x i16> %1
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}
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; CHECK-LABEL: test3_x86_sse41_pblend_w
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; CHECK-NOT: pblendw
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; CHECK: ret
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declare <2 x double> @llvm.x86.sse41.blendpd(<2 x double>, <2 x double>, i32)
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declare <4 x float> @llvm.x86.sse41.blendps(<4 x float>, <4 x float>, i32)
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declare <8 x i16> @llvm.x86.sse41.pblendw(<8 x i16>, <8 x i16>, i32)
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