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86b723434f
(64 to 128-bit) matches against the pattern fragment 'vzmovl_v2i64' (a zero-extended 64-bit load). However, a change in r248784 teaches the instruction combiner that only the lower 64 bits of the input to a 128-bit vcvtph2ps are used. This means the instruction combiner will ordinarily optimize away the upper 64-bit insertelement instruction in the zero-extension and so we no longer select the memory-register form. To fix this a new pattern has been added. Differential Revision: http://reviews.llvm.org/D16067 llvm-svn: 257470
120 lines
4.1 KiB
LLVM
120 lines
4.1 KiB
LLVM
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx,+f16c | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+f16c | FileCheck %s
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define <4 x float> @test_x86_vcvtph2ps_128(<8 x i16> %a0) {
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; CHECK-LABEL: test_x86_vcvtph2ps_128:
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; CHECK-NOT: vmov
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; CHECK: vcvtph2ps
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%res = call <4 x float> @llvm.x86.vcvtph2ps.128(<8 x i16> %a0) ; <<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.vcvtph2ps.128(<8 x i16>) nounwind readonly
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define <8 x float> @test_x86_vcvtph2ps_256(<8 x i16> %a0) {
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; CHECK-LABEL: test_x86_vcvtph2ps_256:
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; CHECK-NOT: vmov
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; CHECK: vcvtph2ps
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%res = call <8 x float> @llvm.x86.vcvtph2ps.256(<8 x i16> %a0) ; <<8 x float>> [#uses=1]
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ret <8 x float> %res
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}
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declare <8 x float> @llvm.x86.vcvtph2ps.256(<8 x i16>) nounwind readonly
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define <8 x float> @test_x86_vcvtph2ps_256_m(<8 x i16>* nocapture %a) nounwind {
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entry:
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; CHECK-LABEL: test_x86_vcvtph2ps_256_m:
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; CHECK-NOT: vmov
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; CHECK: vcvtph2ps (%
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%tmp1 = load <8 x i16>, <8 x i16>* %a, align 16
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%0 = tail call <8 x float> @llvm.x86.vcvtph2ps.256(<8 x i16> %tmp1)
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ret <8 x float> %0
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}
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define <8 x i16> @test_x86_vcvtps2ph_128(<4 x float> %a0) {
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; CHECK-LABEL: test_x86_vcvtps2ph_128:
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; CHECK-NOT: vmov
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; CHECK: vcvtps2ph
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%res = call <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float> %a0, i32 0) ; <<8 x i16>> [#uses=1]
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ret <8 x i16> %res
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}
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declare <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float>, i32) nounwind readonly
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define <8 x i16> @test_x86_vcvtps2ph_256(<8 x float> %a0) {
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; CHECK-LABEL: test_x86_vcvtps2ph_256:
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; CHECK-NOT: vmov
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; CHECK: vcvtps2ph
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%res = call <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float> %a0, i32 0) ; <<8 x i16>> [#uses=1]
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ret <8 x i16> %res
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}
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declare <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float>, i32) nounwind readonly
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define <4 x float> @test_x86_vcvtps2ph_128_scalar(i64* %ptr) {
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; CHECK-LABEL: test_x86_vcvtps2ph_128_scalar:
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; CHECK-NOT: vmov
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; CHECK: vcvtph2ps (%
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%load = load i64, i64* %ptr
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%ins1 = insertelement <2 x i64> undef, i64 %load, i32 0
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%ins2 = insertelement <2 x i64> %ins1, i64 0, i32 1
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%bc = bitcast <2 x i64> %ins2 to <8 x i16>
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%res = tail call <4 x float> @llvm.x86.vcvtph2ps.128(<8 x i16> %bc) #2
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ret <4 x float> %res
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}
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define <4 x float> @test_x86_vcvtps2ph_128_scalar2(i64* %ptr) {
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; CHECK-LABEL: test_x86_vcvtps2ph_128_scalar2:
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; CHECK-NOT: vmov
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; CHECK: vcvtph2ps (%
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%load = load i64, i64* %ptr
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%ins = insertelement <2 x i64> undef, i64 %load, i32 0
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%bc = bitcast <2 x i64> %ins to <8 x i16>
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%res = tail call <4 x float> @llvm.x86.vcvtph2ps.128(<8 x i16> %bc)
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ret <4 x float> %res
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}
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define void @test_x86_vcvtps2ph_256_m(<8 x i16>* nocapture %d, <8 x float> %a) nounwind {
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entry:
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; CHECK-LABEL: test_x86_vcvtps2ph_256_m:
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; CHECK-NOT: vmov
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; CHECK: vcvtps2ph $3, %ymm0, (%
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%0 = tail call <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float> %a, i32 3)
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store <8 x i16> %0, <8 x i16>* %d, align 16
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ret void
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}
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define void @test_x86_vcvtps2ph_128_m(<4 x i16>* nocapture %d, <4 x float> %a) nounwind {
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entry:
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; CHECK-LABEL: test_x86_vcvtps2ph_128_m:
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; CHECK-NOT: vmov
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; CHECK: vcvtps2ph $3, %xmm0, (%
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%0 = tail call <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float> %a, i32 3)
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%1 = shufflevector <8 x i16> %0, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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store <4 x i16> %1, <4 x i16>* %d, align 8
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ret void
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}
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define void @test_x86_vcvtps2ph_128_m2(double* nocapture %hf4x16, <4 x float> %f4x32) #0 {
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entry:
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; CHECK-LABEL: test_x86_vcvtps2ph_128_m2:
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; CHECK-NOT: vmov
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; CHECK: vcvtps2ph $3, %xmm0, (%
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%0 = tail call <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float> %f4x32, i32 3)
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%1 = bitcast <8 x i16> %0 to <2 x double>
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%vecext = extractelement <2 x double> %1, i32 0
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store double %vecext, double* %hf4x16, align 8
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ret void
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}
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define void @test_x86_vcvtps2ph_128_m3(i64* nocapture %hf4x16, <4 x float> %f4x32) #0 {
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entry:
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; CHECK-LABEL: test_x86_vcvtps2ph_128_m3:
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; CHECK-NOT: vmov
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; CHECK: vcvtps2ph $3, %xmm0, (%
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%0 = tail call <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float> %f4x32, i32 3)
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%1 = bitcast <8 x i16> %0 to <2 x i64>
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%vecext = extractelement <2 x i64> %1, i32 0
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store i64 %vecext, i64* %hf4x16, align 8
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ret void
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}
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