llvm-mirror/test/CodeGen/X86/rotate2.ll
Michael Liao 1a80ec900d Add RORX code generation support
llvm-svn: 164674
2012-09-26 08:24:51 +00:00

20 lines
512 B
LLVM

; RUN: llc < %s -march=x86-64 -mcpu=corei7 | grep rol | count 2
define i64 @test1(i64 %x) nounwind {
entry:
%tmp2 = lshr i64 %x, 55 ; <i64> [#uses=1]
%tmp4 = shl i64 %x, 9 ; <i64> [#uses=1]
%tmp5 = or i64 %tmp2, %tmp4 ; <i64> [#uses=1]
ret i64 %tmp5
}
define i64 @test2(i32 %x) nounwind {
entry:
%tmp2 = lshr i32 %x, 22 ; <i32> [#uses=1]
%tmp4 = shl i32 %x, 10 ; <i32> [#uses=1]
%tmp5 = or i32 %tmp2, %tmp4 ; <i32> [#uses=1]
%tmp56 = zext i32 %tmp5 to i64 ; <i64> [#uses=1]
ret i64 %tmp56
}